Ampro Corporation 5001692A manual IDE Interface J6, Pin # Signal Description, Reset, Pdrq, Piow

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Chapter 3

Hardware

IDE Interface (J6)

The IDE device signals are provided through the standard 44-pin, 2mm connector (J6). The IDE interface supports the following features:

Master mode PCI supporting Enhanced IDE devices

Supports two EIDE devices

Full scatter-gather capability

Supports ATAPI compliant devices including DVD

Supports IDE native and ATA compatibility modes

Table 3-9 gives the signals for the 44-pins of the IDE 2mm header.

Table 3-9. IDE Interface Pin/Signal Descriptions (J6)

Pin #

Signal

Description

1

RESET*

Low active hardware reset (RSTDRV inverted)

 

 

 

2

GND

Digital Ground

3

D7

Disk Data 7– These pins (0 to 15) provide disk data.

 

 

 

4

D8

Disk Data 8 – Refer to pin 3, D7, for more information.

 

 

 

5

D6

Disk Data 6– Refer to pin 3, D7, for more information.

 

 

 

6

D9

Disk Data 9 – Refer to pin 3, D7, for more information.

 

 

 

7

D5

Disk Data 5– Refer to pin 3, D7, for more information.

 

 

 

8

D10

Disk Data 10– Refer to pin 3, D7, for more information.

 

 

 

9

D4

Disk Data 4 – Refer to pin 3, D7, for more information.

 

 

 

10

D11

Disk Data 11 – Refer to pin 3, D7, for more information.

11

D3

Disk Data 3 – Refer to pin 3, D7, for more information.

 

 

 

12

D12

Disk Data 12 – Refer to pin 3, D7, for more information.

 

 

 

13

D2

Disk Data 2 – Refer to pin 3, D7, for more information.

14

D13

Disk Data 13 – Refer to pin 3, D7, for more information.

 

 

 

15

D1

Disk Data 1 – Refer to pin 3, D7, for more information.

 

 

 

16

D14

Disk Data 14– Refer to pin 3, D7, for more information.

17

D0

Disk Data 0 – Refer to pin 3, D7, for more information.

 

 

 

18

D15

Disk Data 15 – Refer to pin 3, D7, for more information.

 

 

 

19

GND

Digital Ground

20

Key/GND

Key pin plug/Ground

21

PDRQ

DMA Request – Used for DMA transfers between host and drive (direction of

 

 

transfer controlled by PIOR* and PIOW*). Also used in an asynchronous mode

 

 

with PDACK*. Drive asserts PIRQ when ready to transfer or receive data.

22

GND

Digital Ground

23

PIOW*

Drive I/O Write – Strobe signal for write functions. Negative edge enables data

 

 

from a register or data port of the drive onto the host data bus. Positive edge

 

 

latches data at the host.

24

GND

Digital Ground

CoreModule 420

Reference Manual

27

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Contents CoreModule PC/104 Single Board Computer Reference Manual Audience Assumptions Contents Appendix a Table A-1 Reference Manual CoreModule Chip Specifications SpecificationsAbout This Manual Purpose of this ManualCoreModule 420 Support Products Related Ampro ProductsOther CoreModule Products Other Ampro ProductsChapter Reference Manual CoreModule PC/104 Architecture Product OverviewModule Features Product DescriptionCPU Chapter CRT Bios Block DiagramChip Type Mfg Model Description Function Major Integrated Circuits ICsStpc AtlasConnector Definitions Connectors, Jumpers, and LEDsJack/Plug # Access Description IDEIndicator Definition Jumper # Installed RemovedJumper Definitions LED DefinitionsJP6 JP9 JP7 JP8 JP5 JP4 JP1 Physical Specifications SpecificationsMechanical Specifications DimensionPower Specifications Environmental SpecificationsThermal/Cooling Requirements Reference Manual Overview HardwareMemory CPU U14Use Address Size Memory hole size selected Address Map Interrupt Channel AssignmentsEC00-EC0F 0CFC-0CFFPC/104 Bus Interface P1A,B,C,D Pin # Signal Description P1 Row aPin # Signal Description P1 Row B Pin # Signal Description P1 Row C Pin # Signal Description P1 Row D DRQ5 DRQ6DRQ7 Reset Pin # Signal DescriptionIDE Interface J6 PdrqPdack PiorPirq IDEPCS1CompactFlash Socket J12 Iordy RDYREG ACTFloppy/Parallel Port J4 Floppy Disk Drive PortParallel Port Step SlinPD3 RdataSerial 1 to RS485 Conversion Serial Ports J3, J9, J13, J14Pin # Signal DB9 # Description Usbpwr USB Port J10Usbpn UsbppUtility Interface J5 Ethernet Interface J2 TX+RX+ Video LCD/CRT Interface J11 Tftde TftdclkTftlp FP2User Gpio Signals MiscellaneousReal Time Clock RTC Serial Console Oops! Jumper Bios RecoverySerial Console Bios Setup Watchdog TimerPower Interface J7 Pin Signal DescriptionsPin # Signal Reference Manual CoreModule Bios Setup Accessing Bios Setup VGA DisplayIntroduction Bios Setup Menu Item/Topic Accessing Bios Setup Serial ConsoleBios Setup Opening Screen Main Bios Setup MenuCdrom Bios Configuration ScreenChapter Bios Setup Chapter Bios Setup Chapter Bios Setup USB IRQ none, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or Splash Screen Customization Splash Screen Image RequirementsConverting the Splash Screen File \splashconvert convert.idf On-Board Flash Access and Use Flash Programming RequirementsBuilding the Example Installing the Example Application Flash Boot APIExample Assumptions Method Contact Information Appendix a Technical SupportAppendix a Teka Appendix B Connector Part NumbersGpio 2PH2R44SGAAppendix B Index See also Oops! jumper Bios SetupPost 64MB SdramSerial terminal ANSI-compatible Reference Manual CoreModule