Ampro Corporation 5001692A manual Rdy, Iordy, Reg, Act, Slv

Page 36

Chapter 3

 

Hardware

 

 

 

 

 

 

Pin #

Signal

Description

 

 

 

 

 

 

 

24

NC

Not connected – (IOCS16* = I/O select 16 bit)

 

 

 

 

 

 

 

25

GND

Digital Ground

 

 

 

 

 

 

 

26

NC

Not Connected (Card detect)

 

 

 

 

 

 

 

27

D11

Disk Data 11 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

28

D12

Disk Data 12 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

29

D13

Disk Data 13 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

30

D14

Disk Data 14 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

31

D15

Disk Data 15 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

32

CE2*

Card Enable 2 – This signal, along with CE1*, is used to select the

 

 

 

 

CompactFlash card and indicate to the card when a byte or word operation is

 

 

 

 

being performed. This signal always accesses the odd byte of the word.

 

 

33

NC

Not Connected (VS1*)

 

 

 

 

 

 

 

34

IOR*

I/O Read Strobe – This signal is generated by the host and gates the I/O data onto

 

 

 

 

the bus from the CompactFlash card when the card is configured to use the I/O

 

 

 

 

interface.

 

 

35

IOW*

I/O Write Strobe – This signal is generated by the host and clocks the I/O data on

 

 

 

 

the Card Data bus into the CompactFlash card controller registers when the card

 

 

 

 

is configured to use the I/O interface. The clock occurs on the negative to

 

 

 

 

positive edge of the signal (trailing edge).

 

 

36

Vcc

+5 volts ±5% power supply (WE)

 

 

 

 

 

 

 

37

RDY

Drive Ready – IRQ (IRQ 14) is asserted by drive (CF) when it has a pending

 

 

 

 

interrupt request (PIO transfer of data to or from the drive to the host).

 

 

38

Vcc

+5 volts ±5% power supply

 

 

 

 

 

 

 

39

GND

Grounded (CSEL)

 

 

 

 

 

 

 

40

NC

Not Connected (VS2*)

 

 

 

 

 

 

 

41

IDERst*

IDE Reset – This input signal is the active low hardware reset from the host. If

 

 

 

 

this pin goes high, it is used as the reset signal. This pin is driven high at power-

 

 

 

 

up, causing a reset, and if left high will cause another reset.

 

 

42

IORDY

I/O Channel Ready – When negated, extends the host transfer cycle of any host

 

 

 

 

register access when the drive is not ready to respond to a data transfer request.

 

 

 

 

High impedance if asserted.

 

 

43

NC

Not Connected – (INPACK =Input Acknowledge)

 

 

 

 

 

 

 

44

REG*

Registered/Common Memory Access – Tied High for Common Memory Access.

 

 

 

 

 

 

 

45

ACT/

Drive Active/Slave Present – Tied High for Master/Slave handshake protocol.

 

 

 

SLV

 

 

 

46

NC

Not Connected (PDIAG = Passed Diagnostics)

 

 

 

 

 

 

 

47

D8

Disk Data 8 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

48

D9

Disk Data 9 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

49

D10

Disk Data 10 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

 

50

NC

Not Connected (CD2)

 

 

 

 

 

 

Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic. NC = Not connected, NU = Not used.

30

Reference Manual

CoreModule 420

Image 36
Contents CoreModule PC/104 Single Board Computer Reference Manual Audience Assumptions Contents Appendix a Table A-1 Reference Manual CoreModule Specifications Chip SpecificationsAbout This Manual Purpose of this ManualRelated Ampro Products CoreModule 420 Support ProductsOther CoreModule Products Other Ampro ProductsChapter Reference Manual CoreModule Product Overview PC/104 ArchitectureModule Features Product DescriptionCPU Chapter CRT Block Diagram BiosMajor Integrated Circuits ICs Chip Type Mfg Model Description FunctionStpc AtlasConnectors, Jumpers, and LEDs Connector DefinitionsJack/Plug # Access Description IDEJumper # Installed Removed Indicator DefinitionJumper Definitions LED DefinitionsJP6 JP9 JP7 JP8 JP5 JP4 JP1 Specifications Physical SpecificationsMechanical Specifications DimensionPower Specifications Environmental SpecificationsThermal/Cooling Requirements Reference Manual Hardware OverviewCPU U14 MemoryUse Address Size Memory hole size selected Interrupt Channel Assignments Address Map0CFC-0CFF EC00-EC0FPin # Signal Description P1 Row a PC/104 Bus Interface P1A,B,C,DPin # Signal Description P1 Row B Pin # Signal Description P1 Row C Pin # Signal Description P1 Row D DRQ5 DRQ6DRQ7 Pin # Signal Description ResetIDE Interface J6 PdrqPior PdackPirq IDEPCS1CompactFlash Socket J12 RDY IordyREG ACTFloppy/Parallel Port J4 Floppy Disk Drive PortParallel Port Slin StepPD3 RdataSerial Ports J3, J9, J13, J14 Serial 1 to RS485 ConversionPin # Signal DB9 # Description USB Port J10 UsbpwrUsbpn UsbppUtility Interface J5 Ethernet Interface J2 TX+RX+ Video LCD/CRT Interface J11 Tftdclk TftdeTftlp FP2User Gpio Signals MiscellaneousReal Time Clock RTC Oops! Jumper Bios Recovery Serial ConsoleWatchdog Timer Serial Console Bios SetupPower Interface J7 Pin Signal DescriptionsPin # Signal Reference Manual CoreModule Bios Setup Accessing Bios Setup VGA DisplayIntroduction Accessing Bios Setup Serial Console Bios Setup Menu Item/TopicMain Bios Setup Menu Bios Setup Opening ScreenBios Configuration Screen CdromChapter Bios Setup Chapter Bios Setup Chapter Bios Setup USB IRQ none, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or Splash Screen Customization Splash Screen Image RequirementsConverting the Splash Screen File \splashconvert convert.idf On-Board Flash Access and Use Flash Programming RequirementsBuilding the Example Installing the Example Application Flash Boot APIExample Assumptions Appendix a Technical Support Method Contact InformationAppendix a Appendix B Connector Part Numbers TekaGpio 2PH2R44SGAAppendix B See also Oops! jumper Bios Setup Index64MB Sdram PostSerial terminal ANSI-compatible Reference Manual CoreModule