Texas Instruments TMS380C26 specifications Sddir Direction DIO DMA, Shrq, Sintr

Page 10

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= H)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Interface ± Intel Mode (SI/M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAME

NO.

I/O

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Data Direction. This output provides to the external data buffers a signal indicating the direction

 

 

 

 

 

 

 

 

 

 

 

 

 

in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction input to

 

 

 

 

 

 

 

 

 

 

 

 

 

the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS380C26). When the system interface is NOT involved in a DIO or DMA operation, then SDDIR is

 

SDDIR

38

OUT

high by default.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDDIR

DIRECTION

DIO

DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

output

read

write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

input

write

read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Hold Acknowledge. This pin indicates that the system DMA hold request has been

 

 

 

 

 

 

 

 

 

 

 

 

 

acknowledged. It is internally synchronized to SBCLK (see Note 1).

 

SHLDA/SBGR

37

IN

 

H

= Hold request acknowledged.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= Hold request not acknowledged.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Hold Request. This pin is used to request control of the system bus in preparation for a DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

transfer. This pin is internally synchronized to SBCLK.

 

SHRQ

/SBRQ

 

56

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

= System bus requested.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= System bus not requested.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Interrupt Acknowledge. This signal is from the host processor to acknowledge the interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

request from the TMS380C26.

 

 

 

 

 

 

 

 

 

 

 

24

IN

 

 

 

 

 

 

 

 

SIACK

 

 

 

H

= System interrupt not acknowledged (see Note 1).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= System interrupt acknowledged: the TMS380C26 places its interrupt vector onto the system

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Intel/Motorola Mode Select. The value on this pin specifies the system interface mode.

 

 

 

 

 

 

 

H

= Intel-compatible

interface mode

selected. Intel interface can be 8-bit or 16-bit mode

 

SI

/M

 

 

 

 

35

IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(see S8/SHALT pin description and Note 1.)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= Motorola-compatible interface mode selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Interrupt Request. TMS380C26 activates this output to signal an interrupt request to the host

 

 

 

 

 

 

 

 

 

 

 

 

 

processor.

 

 

 

 

 

 

SINTR

/SIRQ

 

36

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

= Interrupt request by TMS380C26.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= No interrupt request.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Bus Owned. This signal indicates to external devices that TMS380C26 has control of the

 

 

 

 

 

 

 

 

 

 

 

 

 

system bus. This signal drives the enable signal of the bus transceiver chips, which drive the address

 

 

 

 

 

 

 

 

 

 

 

 

 

and bus control signals.

 

 

 

 

 

 

SOWN

59

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

= TMS380C26 does not have control of the system bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= TMS380C26 has control of the system bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPH

62

I/O

System Parity High. The optional odd-parity bit for each address or data byte transmitted over

 

SADH0-SADH7 (see Note 1).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPL

55

I/O

System Parity Low. The optional odd-parity bit for each address or data byte transmitted over

 

SADL0-SADL7 (see Note 1).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

10

POST OFFICE BOX 1443 •HOUSTON, TEXAS

 

77251±1443

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Contents Network Commprocessor Attached System Bus LAN SubsystemPinout PIN Quad Flat Pack TOP ViewDescription Block diagram and signal descriptions Terminal Functions TMS380C26PIN Name Description Maxpl MaxphAX1 AX0 AX3 AX2MOE SresetMreset OUT MrasPrtyen NSELOUT0 NSELOUT1= H SbheShrq Sddir Direction DIO DMASintr SRD SWR= Selects 16-bit mode 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note Syncin= L System Interface ± Motorola Mode SI/MSBHE/ Srnw Sbrq Terminal Functions = LSbgr SirqSdtack SudsSlds Pxtalin FRAQ/TXDNsrt RCVR/RXDTXC LpbkColl Terminal Functions VSS3 VsslVSS1 VSS2 VSS4 VSS5 VSS6Communications processor CP ArchitectureSystem interface SIF Memory interface MIF Protocol handler PHAdapter support function ASF Clock generator CGAdapter-Internal Pointers for Token-Ring² Address DescriptionAdapter-Internal Pointers for Ethernet ² Word Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Byte TransfersSIF Adapter Control Register Sifacl Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value Sifacl RegisterBit 8 Areset Ð Adapter Reset Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 10 Boot Ð Bootstrap CP CodeBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable System Psdmaen Swhrq Swhlda Sinten Interrupt ResultDMA SHRQ/SBRQ Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit See NoteVload IOL Test measurementHigh Low Output Under TestWhen Reference PeriodsClkdiv = Oscout MBCLK1² MBCLK2² Signal Function Static signalsTiming parameter symbology Timing parametersReaches minimum high level 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit HVDDH-RSL 118² Pulse duration High103 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289NMI 126 Delay time from MBCLK1 no longer low to ValidMreset 121 Hold time Valid after MBCLK1 lowMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl MresetMADH0±MADH7 MADL0±MADL7 Maxph Maxpl Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMromen MAL Address Status Column RowAddress Column StatusMaxph Maxpl MADH0±MADH7 Memory bus timing read cycleMcas MOE Maxph MaxplAddress Status Data/Parity MAX0 MAX2 MromenMras Mcas MbiaenMemory bus timing write cycle MAX2 Mromen Enable AddressMAX0, Address Mras Mcas MbenMemory bus timing TMS380C26 releases control of bus Parameter MIN75a 74a MBCLK1 MBCLK2 MbenMddir MAL Mbiaen Mbrq Mbgr Memory bus timing TMS380C26 resumes control of bus Setup time High before MBCLK1 rising edge, bus resumeHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Macs Memory bus timing external bus master read from TMS380C26Hold time Low after MBCLK2 low, external bus master read MAX0 MAX2 Maxph Maxpl MADH0±MADH7 MBCLK1 MBCLK2Mddir Macs MAX0, MAX2 Maxph Maxpl Memory bus timing external bus master write to TMS380C26Data/Pty 73a Memory bus timing Dram refresh timingMADL0±MADL7 Mras Mcas Mref127 128 Xmatch and Xfail timingBit Xmatch XfailRclk Token ring Ð ring interface timingParameter MIN TYP MAX Unit RcvrDrvr Token ring Ð transmitter timing see FigureRclk or Pxtalin 160 159TXD Ethernet timing of clock signalsEthernet timing of Xmit signals TxenRXC Ethernet timing of RCV signals Ð start of frameCRS RXD320 321 Ethernet timing of RCV signals Ð end of frameCrshld 322Norxc Ethernet timing of RCV signals Ð no RXCTXD Txen Data 350TXC TXD JAM80x8x DIO read timing Sras SCS, SrsxSRS0± SRS2 Sbhe Sdben80x8x DIO write timing 281a Valid 264 265 268 256267 272a 280 281 282W 283W 276 279 275 282bSRD, SWR SCS Siack 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse 287 First 286 SecondSdben SRDY²HI-Z SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSRD SWR 80x8x mode bus arbitration timing, SIF takes controlSown SWR SownSRD, SWR Sbbsy ShldaSADL0±SADL7 SPH, SPL This cycle 208b After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² High TwSCKL ±Sbclk Sras 80x8x mode DMA write timing SldsSADH0±SADL7 SPH, SPL SRD HighSADL0±SADH7 Sddir High80x8x mode bus arbitration timing, SIF returns control TW or 80x8x mode bus release timingSbrls Sown 208c68xxx DIO read timing Suds Slds SRS0, SRS1Siack Srnw SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL68xxx DIO write timing Suds Slds SdtackSDTACK² SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Srnw Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack Siack SdtackSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z 275 282a 255Sbgr 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbrqSuds Srnw Sberr Sdtack SbbsySAS, Slds SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPLOn this cycle 208b 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds SldsSAS SADL0±SADH7, SADH0±SADL7 SPL, SPH68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW,SIF HI-Z Sbclk Sbgr SdtackRead HI-Z Write Write ReadSbrls Sown 68xxx mode bus release and error timingSown Sberr Sberr SdtackSbclk Sdtack Sberr Shalt Rerun cycle with delayed start²Normal completion with delayed start² TH B TH E Sbclk Sdtack Sberr Shalt SownJedec NO. Outline Terminals MIN MAX Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM MO±069±ADImportant Notice
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