Texas Instruments TMS380C26 specifications Description

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

description

The TMS380C26 is a single-chip network communications processor (commprocessor) that supports token ring, or Ethernet Local Area Networks (LANs). Either token ring at data rates of 16 Mbps or 4 Mbps, or Ethernet at a data rate of 10 Mbps, can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN subsystems which support both token ring and Ethernet networks, by electrically or physically switched network front-end circuits.

The TMS380C26 conforms to IEEE 802.5±1989 standards and has been verified to be completely IBMToken-Ring compatible. By integrating the essential control building blocks needed on a LAN subsystem card into one device, the TMS380C26 can ensure that this IBM compatability is maintained in silicon.

The TMS380C26 conforms to ISO/IEC 8802±3 (ANSI/IEEE Std 802.3) CSMA/CD standards, and the Ethernet ºBlue Bookº standard.

The high degree of integration of the TMS380C26 makes it a virtual LAN subsystem on a single chip. Protocol handling, host system interfacing, memory interfacing, and communications processing are all provided through the TMS380C26. To complete LAN subsystem design, only the network interface hardware, local memory, and minimal additional components such as PALs and crystal oscillators need to be added.

The TMS380C26 provides a 32-bit system memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TMS380C26 supports direct I/O and a low-cost 8-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally, selectable 80x8x or 68xxx-type host system bus and memory organization add to design flexibility.

The TMS380C26 supports addressing for up to two Megabytes of local memory. This expanded memory capacity can improve LAN subsystem performance by minimizing the frequency of host LAN subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host.

The proprietary CPU used in the TMS380C26 allows protocol software to be downloaded into RAM or stored in ROM in the local memory space. By moving protocols (such as LLC) to the LAN subsystem, overall system performance is increased. This is accomplished due to the the offloading of processing from the host system to the TMS380C26, which may also reduce LAN subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance will be possible.

In addition, the TMS380C26 includes hardware counters that provide realtime error detection and automatic frame buffer management. These counters control system bus retries, burst size, and track host and LAN subsystem buffer status. Previously, these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN subsystem performance is improved.

The TMS380C26 implements a TI-patented Enhanced Address Copy Option (EACO) interface. This interface supports external address checking devices, such as the TMS380SRA Source Routing Accelerator. The TMS380C26 has a 128-word external I/O space in its memory map to support external address-checker devices and other hardware extensions to the TMS380 architecture. Hardware designed in conformance with TI's Specification for External Adapter-bus Devices (SEADs) can map registers into this external I/O space and post interrupts to the TMS380C26.

The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF) as shown in Figure 2.

The TMS380C26 is available in a 132-pin JEDEC plastic quad flat pack and is rated from 0°C to 70°C.

IBM is a registered trademark of International Business Machines Corporation.

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions TMS380C26 Terminal FunctionsPIN Name Description AX3 AX2 MaxphAX1 AX0 MaxplMras SresetMreset OUT MOENSELOUT0 NSELOUT1 PrtyenSbhe = HSddir Direction DIO DMA ShrqSintr SWR SRDSyncin 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note = Selects 16-bit modeSystem Interface ± Motorola Mode SI/M = LSBHE/ Srnw Sirq Terminal Functions = LSbgr SbrqSuds SdtackSlds RCVR/RXD FRAQ/TXDNsrt PxtalinLpbk TXCColl Terminal Functions VSS4 VSS5 VSS6 VsslVSS1 VSS2 VSS3Architecture Communications processor CPSystem interface SIF Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² Byte Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Word TransfersSifacl Register Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value SIF Adapter Control Register SifaclBit 10 Boot Ð Bootstrap CP Code Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 8 Areset Ð Adapter ResetSystem Psdmaen Swhrq Swhlda Sinten Interrupt Result Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputsDmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ DMA SHRQ/SBRQSee Note Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Test measurementHigh Low Vload IOLReference Periods WhenClkdiv = Oscout MBCLK1² MBCLK2² Timing parameters Static signalsTiming parameter symbology Signal FunctionHVDDH-RSL 118² Pulse duration High 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit Reaches minimum high level101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 103121 Hold time Valid after MBCLK1 low 126 Delay time from MBCLK1 no longer low to ValidMreset NMIMreset MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph MaxplMADH0±MADH7 Memory bus timing clocks, MRAS, MCAS, and MAL to Address MADL0±MADL7 Maxph MaxplMromen MAL Column Status Column RowAddress Address StatusMaxph Maxpl Memory bus timing read cycleMcas MOE Maxph Maxpl MADH0±MADH7Mbiaen MAX0 MAX2 MromenMras Mcas Address Status Data/ParityMemory bus timing write cycle Mras Mcas Mben Enable AddressMAX0, Address MAX2 MromenParameter MIN Memory bus timing TMS380C26 releases control of busMBCLK1 MBCLK2 Mben 75a 74aMddir MAL Mbiaen Mbrq Mbgr Setup time High before MBCLK1 rising edge, bus resume Memory bus timing TMS380C26 resumes control of busHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Memory bus timing external bus master read from TMS380C26 MacsHold time Low after MBCLK2 low, external bus master read MBCLK1 MBCLK2 MAX0 MAX2 Maxph Maxpl MADH0±MADH7Mddir Macs Memory bus timing external bus master write to TMS380C26 MAX0, MAX2 Maxph MaxplData/Pty Mcas Mref Memory bus timing Dram refresh timingMADL0±MADL7 Mras 73aXmatch Xfail Xmatch and Xfail timingBit 127 128Rcvr Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rclk160 159 Token ring Ð transmitter timing see FigureRclk or Pxtalin DrvrTxen Ethernet timing of clock signalsEthernet timing of Xmit signals TXDRXD Ethernet timing of RCV signals Ð start of frameCRS RXC322 Ethernet timing of RCV signals Ð end of frameCrshld 320 321Ethernet timing of RCV signals Ð no RXC NorxcTXD Txen JAM 350TXC TXD Data80x8x DIO read timing Sdben SCS, SrsxSRS0± SRS2 Sbhe Sras80x8x DIO write timing 282W 283W 276 279 275 282b Valid 264 265 268 256267 272a 280 281 281a287 First 286 Second 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse SRD, SWR SCS SiackSADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High Sdben SRDY²HI-ZSWR Sown 80x8x mode bus arbitration timing, SIF takes controlSown SRD SWRSbbsy Shlda SRD, SWRSADL0±SADL7 SPH, SPL High TwSCKL ± After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² This cycle 208bSbclk Sras Slds 80x8x mode DMA write timingSddir High SRD HighSADL0±SADH7 SADH0±SADL7 SPH, SPL80x8x mode bus arbitration timing, SIF returns control 208c 80x8x mode bus release timingSbrls Sown TW or68xxx DIO read timing SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SRS0, SRS1Siack Srnw Suds SldsSuds Slds Sdtack 68xxx DIO write timingSADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SDTACK²Siack Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack SCS Srnw Sdtack275 282a 255 SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPLSbrq 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbgrSADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL Sberr Sdtack SbbsySAS, Slds Suds SrnwSuds SAS 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low On this cycle 208bSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlWrite Read Sbclk Sbgr SdtackRead HI-Z Write SIF HI-ZSberr Sdtack 68xxx mode bus release and error timingSown Sberr Sbrls SownTH B TH E Sbclk Sdtack Sberr Shalt Sown Rerun cycle with delayed start²Normal completion with delayed start² Sbclk Sdtack Sberr ShaltMO±069±AD Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec NO. Outline Terminals MIN MAXImportant Notice
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