Texas Instruments TMS380C26 specifications Srd, Swr

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TMS380C26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NETWORK COMMPROCESSOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPWS010A±APRIL 1992±REVISED MARCH 1993

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= H)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Interface ± Intel Mode (SI/M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAME

NO.

I/O

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Memory Address Strobe (see Note 3). This pin used to latch the

 

 

SRSX ± SRS2 register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCS,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

input signals. In a minimum-chip system, SRAS is tied to the SALE output of the System Bus. The

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

latching capability can be defeated since the internal latch for these inputs remains transparent as

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

long as SRAS remains high. This permits SRAS to be pulled high and the signals at the SCS,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRSX ± SRS2, and SBHE to be applied independently of the SALE strobe from the system bus.

 

SRAS/SAS

39

I/O

 

During DMA this pin remains an input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High

 

=

transparent mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low

 

= Holds latched values of

SCS,

SRSX±SRS2, and

SBHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling edge

=

latches SCS, SRSX ± SRS2, and SBHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Read Strobe (see Note 3). Active-low strobe indicating that a read cycle is performed on the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

system bus. This pin is an input during DIO and an output during DMA.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRD

 

 

/SUDS

 

 

 

 

H

=

Read cyle is not occurring.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

=

If DMA: host provides data to system bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If DIO: SIF provides data to system bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Bus Ready (see Note 3).The purpose of this signal is to indicate to the bus master that a data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

transfer is complete. This signal is asynchonous, but during DMA and pseudo-DMA cycles it is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26

 

SRDY/SDTACK

60

I/O

 

is selected for DIO, and an input otherwise.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

=

System bus NOT ready.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

=

Data transfer is complete; system bus is ready.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Reset. This input signal is activated to place the TMS380C26 into a known initial state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

all blocks into the reset state. DMA bus width selection is latched on the rising edge of SRESET.

 

SRESET

 

 

 

25

IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

=

No system reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

=

System reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rising edge

=

Latch bus width for DMA operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRSX

28

 

System Register Select. These inputs select the word or byte to be transferred during a system DIO

 

 

access. The most significant bit is SRSX and the least significant bit is SRS2 (see Note 1).

 

SRS0

27

 

 

IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRS1

 

 

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSb

 

 

 

 

 

 

 

 

 

LSb

 

 

 

SRS2/SBERR

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registered selected =

SRSX

 

SRS0

SRS1

SRS2/SBERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Write Strobe (see Note 3). This pin serves as an active-low write strobe. This pin is an input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during DIO and an output during DMA.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWR

 

/SLDS

 

H

=

Write cycle is not occurring.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

=

If DMA: data to be drivien from SIF to host bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If DIO: on the rising edge, the data is latched and written to the selected register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Extended Address Latch. This output provides the enable pulse used to externally latch the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first

 

SXAL

42

OUT

cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA

 

address counter causes a carry-out of the lower 16 bits). Systems that implement parity on addresses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

extension.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads). 3. Pin should be tied to VCC with a 4.7-kΩpullup resistor.

POST OFFICE BOX 1443 •HOUSTON, TEXAS

11

77251±1443

 

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions AX3 AX2 MaxphAX1 AX0 MaxplMras SresetMreset OUT MOENSELOUT0 NSELOUT1 PrtyenSbhe = HSintr Sddir Direction DIO DMAShrq SWR SRDSyncin 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note = Selects 16-bit modeSBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sirq Terminal Functions = LSbgr SbrqSlds SudsSdtack RCVR/RXD FRAQ/TXDNsrt PxtalinColl LpbkTXC Terminal Functions VSS4 VSS5 VSS6 VsslVSS1 VSS2 VSS3System interface SIF ArchitectureCommunications processor CP Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² Byte Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Word TransfersSifacl Register Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value SIF Adapter Control Register SifaclBit 10 Boot Ð Bootstrap CP Code Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 8 Areset Ð Adapter ResetSystem Psdmaen Swhrq Swhlda Sinten Interrupt Result Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputsDmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ DMA SHRQ/SBRQSee Note Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Test measurementHigh Low Vload IOLClkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Timing parameters Static signalsTiming parameter symbology Signal FunctionHVDDH-RSL 118² Pulse duration High 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit Reaches minimum high level101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 103121 Hold time Valid after MBCLK1 low 126 Delay time from MBCLK1 no longer low to ValidMreset NMIMADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Column Status Column RowAddress Address StatusMaxph Maxpl Memory bus timing read cycleMcas MOE Maxph Maxpl MADH0±MADH7Mbiaen MAX0 MAX2 MromenMras Mcas Address Status Data/ParityMemory bus timing write cycle Mras Mcas Mben Enable AddressMAX0, Address MAX2 MromenParameter MIN Memory bus timing TMS380C26 releases control of busMddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl Mcas Mref Memory bus timing Dram refresh timingMADL0±MADL7 Mras 73aXmatch Xfail Xmatch and Xfail timingBit 127 128Rcvr Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rclk160 159 Token ring Ð transmitter timing see FigureRclk or Pxtalin DrvrTxen Ethernet timing of clock signalsEthernet timing of Xmit signals TXDRXD Ethernet timing of RCV signals Ð start of frameCRS RXC322 Ethernet timing of RCV signals Ð end of frameCrshld 320 321TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc JAM 350TXC TXD Data80x8x DIO read timing Sdben SCS, SrsxSRS0± SRS2 Sbhe Sras80x8x DIO write timing 282W 283W 276 279 275 282b Valid 264 265 268 256267 272a 280 281 281a287 First 286 Second 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse SRD, SWR SCS SiackSADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High Sdben SRDY²HI-ZSWR Sown 80x8x mode bus arbitration timing, SIF takes controlSown SRD SWRSADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR High TwSCKL ± After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² This cycle 208bSbclk Sras Slds 80x8x mode DMA write timingSddir High SRD HighSADL0±SADH7 SADH0±SADL7 SPH, SPL80x8x mode bus arbitration timing, SIF returns control 208c 80x8x mode bus release timingSbrls Sown TW or68xxx DIO read timing SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SRS0, SRS1Siack Srnw Suds SldsSuds Slds Sdtack 68xxx DIO write timingSADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SDTACK²Siack Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack SCS Srnw Sdtack275 282a 255 SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPLSbrq 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbgrSADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL Sberr Sdtack SbbsySAS, Slds Suds SrnwSuds SAS 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low On this cycle 208bSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlWrite Read Sbclk Sbgr SdtackRead HI-Z Write SIF HI-ZSberr Sdtack 68xxx mode bus release and error timingSown Sberr Sbrls SownTH B TH E Sbclk Sdtack Sberr Shalt Sown Rerun cycle with delayed start²Normal completion with delayed start² Sbclk Sdtack Sberr ShaltMO±069±AD Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec NO. Outline Terminals MIN MAXImportant Notice
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