Texas Instruments TMS380C26 Maxph, AX1 AX0, Maxpl, AX3 AX2, MBCLK1 OUT, MBCLK2, Mben, Mbgr, Mbrq

Page 6

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

 

 

 

 

 

 

 

 

Terminal Functions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAME

NO.

I/O

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local Memory Extended Address and Parity High Byte. For the first quarter of a memory cycle this

 

 

 

 

 

 

 

signal carries the extended address bit (AX1); for the second quarter of a memory cycle this signal

 

 

 

 

 

 

 

carries the extended address bit (AX0); and for the last half of the memory cyle this signal carries the

 

MAXPH

130

I/O

parity bit for the high data byte.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Cycle

 

 

 

 

 

 

 

 

 

 

1Q

2Q

3Q

4Q

 

 

 

 

 

 

 

Signal

AX1

AX0

Parity

Parity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local Memory Extended Address and Parity Low Byte. For the first quarter of a memory cycle this

 

 

 

 

 

 

 

signal carries the extended address bit (AX3), for the second quarter of a memory cycle this signal

 

 

 

 

 

 

 

carries extended address bit (AX2); and for the last half of the memory cycle this signal carries the

 

MAXPL

2

I/O

parity bit for the low data byte.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Cycle

 

 

 

 

 

 

 

 

 

 

1Q

2Q

3Q

4Q

 

 

 

 

 

 

 

Signal

AX3

AX2

Parity

Parity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local Bus Clock1 and local Bus Clock 2. These signals are referenced for all local bus transfers.

 

MBCLK1

97

OUT

MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate at 8 MHz for a 64-MHz OSCIN

 

MBCLK2

98

and 6 MHz for a 48-MHz OSCIN, which is twice the memory cycle rate. The MBCLK signals are

 

 

 

 

 

 

 

 

 

always a divide-by-8 of the OSCIN frequency.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer Enable. This signal enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL,

 

 

 

 

 

 

 

and MADL buses during the data phase. This signal is used in conjunction with MDDIR which selects

 

 

 

 

 

 

 

the buffer output direction.

 

 

 

 

 

MBEN

119

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

=

Buffer output disabled.

 

 

 

 

 

 

 

 

 

 

 

L

=

Buffer output enabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

132

OUT

Reserved. Must be left unconnected.

 

 

 

 

MBGR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Burned-In Address Enable. This is an output signal used to provide an output enable for the ROM

 

 

 

 

 

 

 

containing the adapter's Burned-In Address (BIA).

 

 

 

101

OUT

 

 

 

 

 

 

 

 

MBIAEN

 

H

=

This signal is driven high for any WRITE accesses to the addresses between >00.0000 and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

>00.000F, or any accesses (Read/Write) to any other address.

 

 

 

 

 

 

 

L

=

This signal is driven low for any READ from addresses between >00.0000 and >00.000F.

 

 

 

 

 

 

 

 

 

 

 

 

 

131

IN

Reserved. Must be pulled high (see Note 4).

 

 

 

 

MBRQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle

 

 

 

 

 

 

 

following the row address portion of the cycle. This signal is driven low every memory cycle while the

 

 

 

 

 

 

 

column address is valid on MADL0-MADL7, MAXPH, and MAXPL, except when one of the following

 

 

 

 

 

 

 

conditions occurs:

 

 

 

 

 

 

 

 

 

 

 

 

1) When the address accessed is in the BIA ROM (>00.0000 ± >00.000F).

 

MCAS

 

113

OUT

 

2)

When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in

 

 

 

 

 

 

 

 

 

the SIFACL register is zero and an access is made between >00.0010 ± >00.FFFF)

 

 

 

 

 

 

 

 

 

or >1F.0000 ± >1F.FFFF).

 

 

 

 

 

 

 

 

 

 

 

 

3) When the cycle is a refresh cycle, in which case

MCAS

is driven at the start of the cycle before

 

 

 

 

 

 

 

 

 

MRAS (for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CAS-

 

 

 

 

 

 

 

 

 

before-RAS refresh, it may be necessary to disable MCAS with MREF during the refresh

 

 

 

 

 

 

 

 

 

cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Direction. This signal is used as a direction control for bidirectional bus drivers. The signal

 

 

 

 

 

 

 

becomes valid before MBEN active.

 

 

 

 

MDDIR

110

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

=

TMS380C26 memory bus write.

 

 

 

 

 

 

 

 

 

 

L

=

TMS380C26 memory bus read.

 

 

 

NOTE 4: Each pin must be individually tied to VCC with a 1.0-kΩpullup resistor.

6

POST OFFICE BOX 1443 •HOUSTON, TEXAS

 

77251±1443

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Contents Network Commprocessor Attached System Bus LAN SubsystemPinout PIN Quad Flat Pack TOP View Description Block diagram and signal descriptions TMS380C26 Terminal FunctionsPIN Name Description Maxpl MaxphAX1 AX0 AX3 AX2MOE SresetMreset OUT MrasPrtyen NSELOUT0 NSELOUT1= H SbheSddir Direction DIO DMA ShrqSintr SRD SWR= Selects 16-bit mode 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note SyncinSystem Interface ± Motorola Mode SI/M = LSBHE/ Srnw Sbrq Terminal Functions = LSbgr SirqSuds SdtackSlds Pxtalin FRAQ/TXDNsrt RCVR/RXDLpbk TXCColl Terminal Functions VSS3 VsslVSS1 VSS2 VSS4 VSS5 VSS6Architecture Communications processor CPSystem interface SIF Memory interface MIF Protocol handler PHAdapter support function ASF Clock generator CGAdapter-Internal Pointers for Token-Ring² Address DescriptionAdapter-Internal Pointers for Ethernet ² Word Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Byte TransfersSIF Adapter Control Register Sifacl Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value Sifacl RegisterBit 8 Areset Ð Adapter Reset Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 10 Boot Ð Bootstrap CP CodeBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable System Psdmaen Swhrq Swhlda Sinten Interrupt ResultDMA SHRQ/SBRQ Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit See NoteVload IOL Test measurementHigh Low Output Under TestReference Periods WhenClkdiv = Oscout MBCLK1² MBCLK2² Signal Function Static signalsTiming parameter symbology Timing parametersReaches minimum high level 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit HVDDH-RSL 118² Pulse duration High103 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289NMI 126 Delay time from MBCLK1 no longer low to ValidMreset 121 Hold time Valid after MBCLK1 lowMreset MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph MaxplMADH0±MADH7 Memory bus timing clocks, MRAS, MCAS, and MAL to Address MADL0±MADL7 Maxph MaxplMromen MAL Address Status Column RowAddress Column StatusMaxph Maxpl MADH0±MADH7 Memory bus timing read cycleMcas MOE Maxph MaxplAddress Status Data/Parity MAX0 MAX2 MromenMras Mcas MbiaenMemory bus timing write cycle MAX2 Mromen Enable AddressMAX0, Address Mras Mcas MbenMemory bus timing TMS380C26 releases control of bus Parameter MINMBCLK1 MBCLK2 Mben 75a 74aMddir MAL Mbiaen Mbrq Mbgr Setup time High before MBCLK1 rising edge, bus resume Memory bus timing TMS380C26 resumes control of busHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Memory bus timing external bus master read from TMS380C26 MacsHold time Low after MBCLK2 low, external bus master read MBCLK1 MBCLK2 MAX0 MAX2 Maxph Maxpl MADH0±MADH7Mddir Macs Memory bus timing external bus master write to TMS380C26 MAX0, MAX2 Maxph MaxplData/Pty 73a Memory bus timing Dram refresh timingMADL0±MADL7 Mras Mcas Mref127 128 Xmatch and Xfail timingBit Xmatch XfailRclk Token ring Ð ring interface timingParameter MIN TYP MAX Unit RcvrDrvr Token ring Ð transmitter timing see FigureRclk or Pxtalin 160 159TXD Ethernet timing of clock signalsEthernet timing of Xmit signals TxenRXC Ethernet timing of RCV signals Ð start of frameCRS RXD320 321 Ethernet timing of RCV signals Ð end of frameCrshld 322Ethernet timing of RCV signals Ð no RXC NorxcTXD Txen Data 350TXC TXD JAM80x8x DIO read timing Sras SCS, SrsxSRS0± SRS2 Sbhe Sdben80x8x DIO write timing 281a Valid 264 265 268 256267 272a 280 281 282W 283W 276 279 275 282bSRD, SWR SCS Siack 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse 287 First 286 SecondSdben SRDY²HI-Z SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSRD SWR 80x8x mode bus arbitration timing, SIF takes controlSown SWR SownSbbsy Shlda SRD, SWRSADL0±SADL7 SPH, SPL This cycle 208b After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² High TwSCKL ±Sbclk Sras 80x8x mode DMA write timing SldsSADH0±SADL7 SPH, SPL SRD HighSADL0±SADH7 Sddir High80x8x mode bus arbitration timing, SIF returns control TW or 80x8x mode bus release timingSbrls Sown 208c68xxx DIO read timing Suds Slds SRS0, SRS1Siack Srnw SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL68xxx DIO write timing Suds Slds SdtackSDTACK² SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Srnw Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack Siack SdtackSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z 275 282a 255Sbgr 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbrqSuds Srnw Sberr Sdtack SbbsySAS, Slds SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPLOn this cycle 208b 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds SldsSAS SADL0±SADH7, SADH0±SADL7 SPL, SPH68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW,SIF HI-Z Sbclk Sbgr SdtackRead HI-Z Write Write ReadSbrls Sown 68xxx mode bus release and error timingSown Sberr Sberr SdtackSbclk Sdtack Sberr Shalt Rerun cycle with delayed start²Normal completion with delayed start² TH B TH E Sbclk Sdtack Sberr Shalt SownJedec NO. Outline Terminals MIN MAX Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM MO±069±ADImportant Notice
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