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| TMS380C26 | |
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| NETWORK COMMPROCESSOR | |||
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| SPWS010A±APRIL 1992±REVISED MARCH 1993 | |||
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| Terminal Functions (continued) | ||||||||
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| PIN NAME | NO. | I/O |
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| DESCRIPTION | ||||||||
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| Memory Output Enable. This signal is used to enable the outputs of the DRAM memory during a read | |||||||||
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| cycle. This signal is high for EPROM or BIA ROM read cycles. | |||||||||
| MOE |
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| 118 | OUT |
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| H | = | Disable DRAM outputs. |
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| L | = | Enable DRAM outputs. |
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| Row Address Strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. This | |||||||||
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| signal is driven low every memory cycle while the row address is valid on | |||||||||
| MRAS | 115 | OUT | |||||||||||||||
| and MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh | |||||||||||||||||
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| address is valid on | |||||||||
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| DRAM Refresh Cycle in Progress. This signal is used to indicate that a DRAM refresh cycle is | |||||||||
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| occurring. It is also used for disabling MCAS to all DRAMs that do not use a | CAS | ||||||||
| MREF | 102 | OUT |
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| H | = | DRAM refresh cycle in process. | |||||||
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| L | = | Not a DRAM refresh cycle. | |||||||
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| Memory Bus Reset. This is a reset signal generated when either the ARESET bit in the SIFACL | |||||||||
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| register is set or the | SRESET | pin is asserted. This signal is used for resetting external local bus glue | |||||||
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| logic. |
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| MRESET | 99 | OUT |
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| H | = | External logic not reset. |
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| L | = | External logic reset. |
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| ROM Enable. During the first 5/16 of the memory cycle, this signal is used to provide a chip select | |||||||||
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| for ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not | |||||||||
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| RAM). It can be latched by MAL. It goes low for any read from addresses >00.0010 ± >00.FFFF or | |||||||||
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| >1F.0000 ± >1F.FFFF when the Boot bit in the SIFACL register is zero. It stays high for writes to these | |||||||||
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| addresses, accesses of other addresses, or accesses of any address when the BOOT bit is one. | |||||||||
| MROMEN |
| 105 | OUT | During the final three quarters of the memory cycle, it outputs the A13 address signal for interfacing | |||||||||||||
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| to a BIA ROM. This means MBIAEN, MAX0, ROMEN, and MAX2 together form a glueless interface | |||||||||
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| for the BIA ROM. |
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| H | = | ROM disabled. |
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| L | = | ROM enabled. |
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| Local Memory Write. This signal is used to specify a write cycle on the local memory bus. The data | |||||||||
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| on the | |||||||||
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| the falling edge MW, while SRAMs latch data on the rising edge of MW. | |||||||||
| MW | 114 | OUT | |||||||||||||||
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| H | = | Not a local memory write cycle. | |||||||
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| L | = | Local memory write cycle. | |||||||
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| 15 | IN | ||||||||||
| NMI |
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| OSCIN | 107 | IN | External Oscillator Input. This line provides the clock frequency to the TMS380C26 for a | ||||||||||||||
| internal bus. OSCIN should be 64 a MHz signal (see Note 5). | |||||||||||||||||
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| Oscillator Output. With OSCIN at 64 MHz and CLKDIV pulled high, this pin provides an 8 MHz output | |||||||||
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| which can be used by TMS3054 for 4 Mbps operation without the need for an additional crystal. | |||||||||
| OSCOUT | 96 | OUT | CLKDIV | OSCOUT |
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| L |
| Reserved | (Reserved) | |||||
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| H |
| OSCIN/8 | (if OSCIN = 64 MHz, then OSCOUT = 8 MHz). |
NOTE 5: Pin has an expanded input voltage specification.
POST OFFICE BOX 1443 •HOUSTON, TEXAS | 7 |
77251±1443 |
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