Texas Instruments TMS380C26 specifications Terminal Functions, PIN Name Description

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TMS380C26

 

 

 

 

 

 

 

 

 

 

 

NETWORK COMMPROCESSOR

 

 

 

 

 

 

 

 

 

 

 

SPWS010A±APRIL 1992±REVISED MARCH 1993

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAME

NO.

I/O

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bootstrap. The value on this pin is loaded into the BOOT bit of the SIFACL register at reset (i.e., when

 

 

 

 

 

 

 

the SRESET pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value.

 

 

 

 

 

 

 

This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters

 

BTSTRP

23

IN

are RAM then the TMS380C26 is denied access to the local memory bus until the CPHALT bit in the

 

SIFACL register is cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

= Chapters 0 and 31 of local memory are RAM-based (see Note 1).

 

 

 

 

 

 

 

L

= Chapters 0 and 31 of local memory are ROM-based.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Divider Select. This pin must be pulled high

 

 

 

CLKDIV

19

IN

H

= Indicates 64-MHz OSCIN (see Note 3).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

= Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

EXTINT0

 

 

 

 

 

 

 

 

 

 

EXTINT1

13

IN

Reserved; must be pulled high (see Note 4).

 

 

 

 

EXTINT2

12

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTINT3

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

104

IN

Reserved. Must be tied low (see Note 2).

 

 

 

 

MACS

 

 

 

 

 

 

 

 

 

 

 

MADH0

129

 

Local memory Address, Data and Status Bus ± high byte. For the first quarter of the local memory

 

MADH1

128

 

cycle these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status

 

MADH2

127

 

bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0

 

MADH3

126

I/O

and the least significant bit is MADH7.

 

 

 

 

MADH4

123

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MADH5

122

 

 

 

 

Memory Cycle

 

 

 

MADH6

121

 

 

 

1Q

2Q

3Q

4Q

 

MADH7

120

 

Signal

AX4,A0±A6

Status

D0±D7

D0±D7

 

 

 

 

 

 

 

MADL0

10

 

Local Memory Address, Data and Status Bus ± low byte. For the first quarter of the local memory

 

MADL1

9

 

cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits

 

MADL2

8

 

AX4 and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most

 

MADL3

7

I/O

significant bit is MADL0 and the least significant bit is MADL7.

 

MADL4

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MADL5

5

 

 

 

 

Memory Cycle

 

 

 

 

MADL6

4

 

 

 

1Q

2Q

3Q

4Q

 

MADL7

3

 

Signal

A7±A14

AX4,A0±A6

D8±D15

D8±D15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Address Latch. This is a strobe signal for sampling the address at the start of the memory

 

 

 

 

 

 

 

cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,

 

 

 

 

 

 

 

MAX2, MAXPL, MADH0-MADH7, and MADL0-MADL7. Three 8-bit transparent latches can therefore

 

MAL

 

103

OUT

be used to retain a 20-bit static address throughout the cycle.

 

 

 

 

 

 

 

 

 

Rising edge

= No signal latching.

 

 

 

 

 

 

 

 

 

 

Falling edge

= Allows the above address signals to be latched.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local Memory Extended Address Bit. This signal drives AX0 at ROW address time and it drives A12

 

 

 

 

 

 

 

at COL address and DATA time for all cycles. This signal can be latched by MRAS. Driving A12 eases

 

MAX0

111

OUT

interfacing to a BIA ROM.

 

 

 

 

 

 

 

 

Memory Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1Q

2Q

3Q

4Q

 

 

 

 

 

 

 

 

Signal

AX0

A12

A12

A12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local Memory Extended Address Bit. This signal drives AX2 at ROW address time, which can be

 

 

 

 

 

 

 

latched by MRAS, and A14 at COL address, and DATA time for all cycles. Driving A14 eases

 

MAX2

112

OUT

interfacing to a BIA ROM.

 

 

 

 

 

 

 

 

Memory Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1Q

2Q

3Q

4Q

 

 

 

 

 

 

 

 

Signal

AX2

A14

A14

A14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

2.Pin should be connected to ground.

3.Pin should be tied to VCC with a 4.7-kΩpullup resistor.

4.Each pin must be individually tied to VCC with a 1.0-kΩpullup resistor.

POST OFFICE BOX 1443 •HOUSTON, TEXAS

5

77251±1443

 

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions AX1 AX0 MaxphMaxpl AX3 AX2Mreset OUT SresetMOE MrasNSELOUT0 NSELOUT1 PrtyenSbhe = HSintr Sddir Direction DIO DMAShrq SWR SRD= Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode SyncinSBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sbgr Terminal Functions = LSbrq SirqSlds SudsSdtack Nsrt FRAQ/TXDPxtalin RCVR/RXDColl LpbkTXC Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6System interface SIF ArchitectureCommunications processor CP Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte TransfersBit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl RegisterBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP CodeBit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt ResultSysteminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See NoteHigh Low Test measurementVload IOL Output Under TestClkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Timing parameter symbology Static signalsSignal Function Timing parametersParameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration HighMinimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 lowMADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Address Column RowAddress Status Column StatusMcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph MaxplMras Mcas MAX0 MAX2 MromenAddress Status Data/Parity MbiaenMemory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas MbenParameter MIN Memory bus timing TMS380C26 releases control of busMddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas MrefBit Xmatch and Xfail timing127 128 Xmatch XfailParameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk RcvrRclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD TxenCRS Ethernet timing of RCV signals Ð start of frameRXC RXDCrshld Ethernet timing of RCV signals Ð end of frame320 321 322TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc TXC TXD 350Data JAM80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 SecondSddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR SownSADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ±Sbclk Sras Slds 80x8x mode DMA write timingSADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSuds Slds Sdtack 68xxx DIO write timingSDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack SdtackSdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr SbrqSAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlRead HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write ReadSown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr SdtackNormal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±ADImportant Notice
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