Texas Instruments TMS380C26 specifications = L, System Interface ± Motorola Mode SI/M, SBHE/ Srnw

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TMS380C26

 

 

 

 

 

 

NETWORK COMMPROCESSOR

 

 

 

 

 

 

 

 

SPWS010A±APRIL 1992±REVISED MARCH 1993

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (continued)

 

 

 

 

 

 

 

= L)

 

 

 

 

 

System Interface ± Motorola Mode (SI/M

 

 

 

 

 

 

 

 

PIN NAME

NO.

I/O

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

SADH0

73

 

 

 

 

 

 

 

SADH1

72

 

System Address/Data BusÐhigh byte (see Note 1).These lines make up the most significant byte

 

SADH2

71

 

of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit

 

SADH3

70

I/O

is SADH0, and the least significant bit is SADH7.

 

SADH4

69

 

 

 

 

 

 

 

Address Multiplexing ² : Bits 31 ± 24 and bits 15 ± 8.

 

SADH5

68

 

 

SADH6

64

 

Data Multiplexing ² : Bits 15 ± 8.

 

SADH7

63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SADL0

54

 

 

 

 

 

 

 

SADL1

53

 

System Address/Data BusÐlow byte (see Note 1). These lines make up the least significant byte of

 

SADL2

52

 

each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is

 

SADL3

49

I/O

SADL0, and the least significant bit is SADL7.

 

SADL4

48

 

 

 

 

 

 

 

Address Multiplexing ² : Bits 23 ± 16 and bits 7 ± 0.

 

SADL5

47

 

 

SADL6

46

 

Data Multiplexing ² : Bits 7 ± 0.

 

SADL7

45

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Address Latch Enable. This is the enable pulse used to externally latch the 16 LSBs of the

 

SALE

43

OUT

address from the SADH0 ± SADH7 and SADL0 ± SADL7 buses at the start of the DMA cycle.

 

Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for

 

 

 

 

 

 

 

 

 

 

the latched address.

 

 

 

 

 

 

 

 

 

 

 

System Bus Busy. The TMS380C26 samples the value on this pin during arbitration. The sample has

 

 

 

 

 

one of (2) two values (see Note 1):

 

SBBSY

 

31

IN

 

 

 

 

 

 

 

 

 

 

H

= Not busy. The TMS380C26 may become Bus Master if the grant condition is met.

 

 

 

 

 

L

= Busy. The TMS380C26 cannot become Bus Master.

 

 

 

 

 

 

 

SBCLK

44

IN

System Bus Clock. The TMS380C26 requires the external clock to synchronize its bus timings for

 

all DMA transfers.

 

 

 

 

 

System Read Not Write. This pin serves as a control signal to indicate a read or write cycle.

SBHE/SRNW

57

I/O

H

=

Read Cycle (see Note 1).

 

 

 

 

 

 

L

=

Write Cycle

System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is NOT perfoming DMA. This signal is internally synchronized to SBCLK.

 

SBRLS

30

IN

 

 

 

 

 

 

 

 

 

H

=

The TMS380C26 can hold onto the system bus (see Note 1).

 

 

 

 

 

 

L

=

The TMS380C26 should release the system bus upon completion of current DMA cycle. If the

 

 

 

 

 

 

 

 

DMA transfer is not yet complete, the SIF will rearbitrate for the system bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

System Chip Select. Activates the system interface of TMS380C26 for a DIO read or write.

 

 

 

29

IN

 

 

 

 

SCS

 

 

H

=

Not selected (see Note 1).

 

 

 

 

 

 

 

 

 

 

 

 

L

=

Selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

System Data Bus Enable. This output signals to the external data buffers to begin driving data. This

 

 

 

 

 

 

output is activated during both DIO and DMA.

 

SDBEN

 

58

OUT

 

 

 

 

 

 

 

 

 

H

=

Keep external data buffers in high-impedance state.

L= Cause external data buffers to begin driving data.

²Typical bit ordering for Intel and Motorola processor buses.

NOTE 1: Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads).

POST OFFICE BOX 1443 HOUSTON, TEXAS

13

77251±1443

 

Image 13
Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions Terminal Functions TMS380C26PIN Name Description AX1 AX0 MaxphMaxpl AX3 AX2Mreset OUT SresetMOE MrasNSELOUT0 NSELOUT1 PrtyenSbhe = HShrq Sddir Direction DIO DMASintr SWR SRD= Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode Syncin= L System Interface ± Motorola Mode SI/MSBHE/ Srnw Sbgr Terminal Functions = LSbrq SirqSdtack SudsSlds Nsrt FRAQ/TXDPxtalin RCVR/RXDTXC LpbkColl Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6Communications processor CP ArchitectureSystem interface SIF Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte TransfersBit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl RegisterBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP CodeBit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt ResultSysteminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See NoteHigh Low Test measurementVload IOL Output Under TestWhen Reference PeriodsClkdiv = Oscout MBCLK1² MBCLK2² Timing parameter symbology Static signalsSignal Function Timing parametersParameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration HighMinimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 lowMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl MresetMADH0±MADH7 MADL0±MADL7 Maxph Maxpl Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMromen MAL Address Column RowAddress Status Column StatusMcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph MaxplMras Mcas MAX0 MAX2 MromenAddress Status Data/Parity MbiaenMemory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas MbenParameter MIN Memory bus timing TMS380C26 releases control of bus75a 74a MBCLK1 MBCLK2 MbenMddir MAL Mbiaen Mbrq Mbgr Memory bus timing TMS380C26 resumes control of bus Setup time High before MBCLK1 rising edge, bus resumeHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Macs Memory bus timing external bus master read from TMS380C26Hold time Low after MBCLK2 low, external bus master read MAX0 MAX2 Maxph Maxpl MADH0±MADH7 MBCLK1 MBCLK2Mddir Macs MAX0, MAX2 Maxph Maxpl Memory bus timing external bus master write to TMS380C26Data/Pty MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas MrefBit Xmatch and Xfail timing127 128 Xmatch XfailParameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk RcvrRclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD TxenCRS Ethernet timing of RCV signals Ð start of frameRXC RXDCrshld Ethernet timing of RCV signals Ð end of frame320 321 322Norxc Ethernet timing of RCV signals Ð no RXCTXD Txen TXC TXD 350Data JAM80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 SecondSddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR SownSRD, SWR Sbbsy ShldaSADL0±SADL7 SPH, SPL 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ±Sbclk Sras Slds 80x8x mode DMA write timingSADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSuds Slds Sdtack 68xxx DIO write timingSDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack SdtackSdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr SbrqSAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlRead HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write ReadSown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr SdtackNormal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±ADImportant Notice