Texas Instruments TMS380C26 specifications 68xxx DIO write timing, Suds Slds Sdtack

Page 77

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

68xxx DIO write timing

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

255

Delay from

 

 

 

 

 

 

 

 

 

 

 

 

low to either

 

 

 

 

 

 

 

 

 

 

SUDS or

 

 

 

high

 

15

 

ns

SDTACK

 

 

SCS,

 

 

SLDS

 

 

262

Setup of write data valid before

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

no longer low

 

25

 

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

263

Hold of write data valid after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

high

 

25

 

ns

SUDS

 

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

267§

Setup of register address before

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

no longer high (see Note 21)

 

15

 

ns

SUDS

SLDS

 

 

268

Hold of register address valid after

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

no longer low (see Note 22)

 

0

 

ns

SUDS

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

272

Setup of SRNW before

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

no longer high (see Note 21)

 

15

 

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

272a

Setup of inactive

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

high to active data strobe no longer high

 

55

 

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

273

Hold of SRNW after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

high

 

0

 

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

273a

Hold of inactive

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

high after active data strobe high

 

55

 

ns

SUDS

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

275

Delay from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

 

high (see Note 21)

 

 

35

ns

SCS,

 

SUDS

SLDS

SDTACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Delay from

 

 

 

 

 

 

 

 

 

 

 

low in the first DIO access to the SIF register to

 

low in the

 

 

 

276³

SDTACK

 

SDTACK

 

4000

ns

immediately following access to the SIF

 

 

279²

Delay from

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

 

 

 

 

high impedance

 

 

65

ns

SUDS

SLDS

SDTACK

 

 

280

Delay from

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

low to SDDIR low (see Note 21)

 

 

25

ns

SUDS

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

281

Delay from

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

high to SDDIR high (see Note 21)

 

 

55

ns

SUDS

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

281a

Hold of SDDIR low after

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

no longer active (see Note 21)

 

0

 

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If SIF register is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ready (no waiting

0

35

 

282b

Delay from SDBEN low to SDTACK low (see TMS380 Second Generation Token-

required)

 

 

ns

Ring User's Guide, SPWU005, subsection 3.4.1.1.1)

If SIF register is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not ready (waiting

0

4000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

required)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

282W

Delay from SDDIR low to

SDBEN

low

 

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

283W

Delay from

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

high to

 

 

 

 

 

 

 

 

 

 

 

 

no longer low

 

 

25

ns

SUDS

SLDS

SDBEN

 

 

 

 

 

 

 

 

 

 

286

Pulse duration,

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

high between DIO accesses (see Note 21)

 

55

 

ns

SUDS

SLDS

 

 

²This specification is provided as an aid to board design.

³This specification has been characterized to meet stated value.

§ It is the later of SRD and SWR or SCS low that indicates the start of the cycle.

NOTES: 21. The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

22.In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0±SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0±SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters 266a and 264 are irrelevant, and parameter 268 must be met.

POST OFFICE BOX 1443 •HOUSTON, TEXAS

77

77251±1443

 

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions AX1 AX0 MaxphMaxpl AX3 AX2Mreset OUT SresetMOE MrasNSELOUT0 NSELOUT1 PrtyenSbhe = HSintr Sddir Direction DIO DMAShrq SWR SRD= Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode SyncinSBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sbgr Terminal Functions = LSbrq SirqSlds SudsSdtack Nsrt FRAQ/TXDPxtalin RCVR/RXDColl LpbkTXC Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6System interface SIF ArchitectureCommunications processor CP Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte TransfersBit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl RegisterBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP CodeBit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt ResultSysteminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See NoteHigh Low Test measurementVload IOL Output Under TestClkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Timing parameter symbology Static signalsSignal Function Timing parametersParameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration HighMinimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 lowMADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Address Column RowAddress Status Column StatusMcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph MaxplMras Mcas MAX0 MAX2 MromenAddress Status Data/Parity MbiaenMemory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas MbenParameter MIN Memory bus timing TMS380C26 releases control of busMddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas MrefBit Xmatch and Xfail timing127 128 Xmatch XfailParameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk RcvrRclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD TxenCRS Ethernet timing of RCV signals Ð start of frameRXC RXDCrshld Ethernet timing of RCV signals Ð end of frame320 321 322TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc TXC TXD 350Data JAM80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 SecondSddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR SownSADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ±Sbclk Sras Slds 80x8x mode DMA write timingSADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSuds Slds Sdtack 68xxx DIO write timingSDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack SdtackSdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr SbrqSAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlRead HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write ReadSown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr SdtackNormal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±ADImportant Notice
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