Texas Instruments TMS380C26 68xxx mode DMA read timing, On this cycle 208b, Suds SAS

Page 83

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

68xxx mode DMA read timing

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

205

Setup of input data valid before SBCLK in T3 cycle no longer high

15

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

206

Hold of input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met

15

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

207a

Hold of input data valid after data strobe no longer low

0

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

207b

Hold of input data valid after

 

 

 

 

 

 

 

 

 

no longer low

0

 

ns

SDBEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup of asynchronous input

 

 

 

 

 

 

 

 

 

 

 

before SBCLK no longer high to guarantee recognition

 

 

 

208a

SDTACK

 

15

 

ns

on this cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

208b

Hold of asynchronous input

 

 

 

 

 

 

 

 

 

 

 

after SBCLK low to guarantee recognition on this cycle

15

 

ns

SDTACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tc(SCK)+

 

 

209

Pulse duration, SAS, SUDS, and SLDS high

 

ns

tw(SCKL) ± 25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

210

Delay from SBCLK high in T2 cycle to

 

 

 

 

 

 

 

and

 

 

 

active

 

25

ns

SUDS

 

SLDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

212

Delay from SBCLK low to address valid

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

214²

Delay from SBCLK low in T2 cycle to SAD high-impedance

 

25

ns

215

Pulse duration, SALE and SXAL high

tc(SCK) ± 25

 

ns

216

Delay from SBCLK high to SALE or SXAL high

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

216a

Hold of SALE or SXAL low after

 

 

 

 

 

 

 

 

 

and

 

 

 

 

 

high

tw(SCKL) ± 15

 

ns

SUDS

SAS

 

217

Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

218

Hold of address valid after SALE, SXAL low

tw(SCKH) ± 15

 

ns

222

Delay from SBCLK high to

 

 

 

 

 

low

 

25

ns

SAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

223R

Delay from SBCLK low in T4 cycle to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and

 

high (see Note 25)

 

25

ns

SUDS,

 

SLDS,

SAS

 

 

 

 

 

 

 

 

 

 

 

 

225R

Delay from SBCLK low in T4 cycle to

 

 

 

 

 

 

 

 

 

 

high

 

25

ns

SDBEN

 

 

 

 

 

 

 

 

 

 

 

 

229²

Hold of SAD high-impedance after SBCLK low in T4 cycle

0

 

ns

233

Setup of address valid before SALE or SXAL no longer high

tw(SCKL) ± 15

 

ns

233a

Setup of address valid before

 

 

 

 

no longer high

tw(SCKL) ± 15

 

ns

SAS

 

237R

Delay from SBCLK high in the T2 cycle to

 

 

 

 

 

 

 

 

low

 

25

ns

SDBEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2tc(SCK)+

 

 

239

Pulse duration, SAS, SUDS, and SLDS

 

ns

tw(SCKH) ± 30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

247

Setup of data valid before

 

 

 

 

 

 

 

 

 

 

low if parameter 208a not met

0

 

ns

SDTACK

 

² This specification has been characterized to meet stated value.

NOTE 25: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.

POST OFFICE BOX 1443 •HOUSTON, TEXAS

83

77251±1443

 

Page 82 Page 84
Image 83
Page 82 Page 84
Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions AX3 AX2 MaxphAX1 AX0 MaxplMras SresetMreset OUT MOENSELOUT0 NSELOUT1 PrtyenSbhe = HSintr Sddir Direction DIO DMAShrq SWR SRDSyncin 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note = Selects 16-bit modeSBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sirq Terminal Functions = LSbgr SbrqSlds SudsSdtack RCVR/RXD FRAQ/TXDNsrt PxtalinColl LpbkTXC Terminal Functions VSS4 VSS5 VSS6 VsslVSS1 VSS2 VSS3System interface SIF ArchitectureCommunications processor CP Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² Byte Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Word TransfersSifacl Register Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value SIF Adapter Control Register SifaclBit 10 Boot Ð Bootstrap CP Code Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 8 Areset Ð Adapter ResetSystem Psdmaen Swhrq Swhlda Sinten Interrupt Result Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputsDmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ DMA SHRQ/SBRQSee Note Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Test measurementHigh Low Vload IOLClkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Timing parameters Static signalsTiming parameter symbology Signal FunctionHVDDH-RSL 118² Pulse duration High 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit Reaches minimum high level101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 103121 Hold time Valid after MBCLK1 low 126 Delay time from MBCLK1 no longer low to ValidMreset NMIMADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Column Status Column RowAddress Address StatusMaxph Maxpl Memory bus timing read cycleMcas MOE Maxph Maxpl MADH0±MADH7Mbiaen MAX0 MAX2 MromenMras Mcas Address Status Data/ParityMemory bus timing write cycle Mras Mcas Mben Enable AddressMAX0, Address MAX2 MromenParameter MIN Memory bus timing TMS380C26 releases control of busMddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl Mcas Mref Memory bus timing Dram refresh timingMADL0±MADL7 Mras 73aXmatch Xfail Xmatch and Xfail timingBit 127 128Rcvr Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rclk160 159 Token ring Ð transmitter timing see FigureRclk or Pxtalin DrvrTxen Ethernet timing of clock signalsEthernet timing of Xmit signals TXDRXD Ethernet timing of RCV signals Ð start of frameCRS RXC322 Ethernet timing of RCV signals Ð end of frameCrshld 320 321TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc JAM 350TXC TXD Data80x8x DIO read timing Sdben SCS, SrsxSRS0± SRS2 Sbhe Sras80x8x DIO write timing 282W 283W 276 279 275 282b Valid 264 265 268 256267 272a 280 281 281a287 First 286 Second 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse SRD, SWR SCS SiackSADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High Sdben SRDY²HI-ZSWR Sown 80x8x mode bus arbitration timing, SIF takes controlSown SRD SWRSADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR High TwSCKL ± After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² This cycle 208bSbclk Sras Slds 80x8x mode DMA write timingSddir High SRD HighSADL0±SADH7 SADH0±SADL7 SPH, SPL80x8x mode bus arbitration timing, SIF returns control 208c 80x8x mode bus release timingSbrls Sown TW or68xxx DIO read timing SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SRS0, SRS1Siack Srnw Suds SldsSuds Slds Sdtack 68xxx DIO write timingSADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SDTACK²Siack Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack SCS Srnw Sdtack275 282a 255 SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPLSbrq 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbgrSADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL Sberr Sdtack SbbsySAS, Slds Suds SrnwSuds SAS 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low On this cycle 208bSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlWrite Read Sbclk Sbgr SdtackRead HI-Z Write SIF HI-ZSberr Sdtack 68xxx mode bus release and error timingSown Sberr Sbrls SownTH B TH E Sbclk Sdtack Sberr Shalt Sown Rerun cycle with delayed start²Normal completion with delayed start² Sbclk Sdtack Sberr ShaltMO±069±AD Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec NO. Outline Terminals MIN MAXImportant Notice
Top Page Image Contents