Texas Instruments TMS380C26 Test measurement, High Low, Vload IOL, Output Under Test, Ioh

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. These levels are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 volts, and the level at which the signal is said to be low is 0.8 volts. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 volts, and the level at which the signal is said to be high is 2 volts, as shown below.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically 1.5 ns.

2 V (High)

0.8 V (Low)

test measurement

The test load circuit shown in Figure 4 represents the programmable load of the tester pin electronics which are used to verify timing parameters of TMS380C26 output signals.

Tester Pin Electronics

VLOAD

IOL

Output

Under

Test

CT

IOH

Where: IOL = 2.0 mA DC level verification (all outputs) IOH = 400 ∝A (all outputs)

VLOAD = 1.5 V typical DC level verification

0.7V typical timing verification CT = 65 pF typical load circuit capacitance

Figure 4. Test Load Circuit

POST OFFICE BOX 1443 •HOUSTON, TEXAS	31
77251±1443

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions Terminal Functions TMS380C26PIN Name Description AX3 AX2 MaxphAX1 AX0 MaxplMras SresetMreset OUT MOENSELOUT0 NSELOUT1 PrtyenSbhe = HShrq Sddir Direction DIO DMASintr SWR SRDSyncin 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note = Selects 16-bit mode= L System Interface ± Motorola Mode SI/MSBHE/ Srnw Sirq Terminal Functions = LSbgr SbrqSdtack SudsSlds RCVR/RXD FRAQ/TXDNsrt PxtalinTXC LpbkColl Terminal Functions VSS4 VSS5 VSS6 VsslVSS1 VSS2 VSS3Communications processor CP ArchitectureSystem interface SIF Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² Byte Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Word TransfersSifacl Register Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value SIF Adapter Control Register SifaclBit 10 Boot Ð Bootstrap CP Code Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 8 Areset Ð Adapter ResetSystem Psdmaen Swhrq Swhlda Sinten Interrupt Result Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputsDmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ DMA SHRQ/SBRQSee Note Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Test measurementHigh Low Vload IOLWhen Reference PeriodsClkdiv = Oscout MBCLK1² MBCLK2² Timing parameters Static signalsTiming parameter symbology Signal FunctionHVDDH-RSL 118² Pulse duration High 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit Reaches minimum high level101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 103121 Hold time Valid after MBCLK1 low 126 Delay time from MBCLK1 no longer low to ValidMreset NMIMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl MresetMADH0±MADH7 MADL0±MADL7 Maxph Maxpl Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMromen MAL Column Status Column RowAddress Address StatusMaxph Maxpl Memory bus timing read cycleMcas MOE Maxph Maxpl MADH0±MADH7Mbiaen MAX0 MAX2 MromenMras Mcas Address Status Data/ParityMemory bus timing write cycle Mras Mcas Mben Enable AddressMAX0, Address MAX2 MromenParameter MIN Memory bus timing TMS380C26 releases control of bus75a 74a MBCLK1 MBCLK2 MbenMddir MAL Mbiaen Mbrq Mbgr Memory bus timing TMS380C26 resumes control of bus Setup time High before MBCLK1 rising edge, bus resumeHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Macs Memory bus timing external bus master read from TMS380C26Hold time Low after MBCLK2 low, external bus master read MAX0 MAX2 Maxph Maxpl MADH0±MADH7 MBCLK1 MBCLK2Mddir Macs MAX0, MAX2 Maxph Maxpl Memory bus timing external bus master write to TMS380C26Data/Pty Mcas Mref Memory bus timing Dram refresh timingMADL0±MADL7 Mras 73aXmatch Xfail Xmatch and Xfail timingBit 127 128Rcvr Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rclk160 159 Token ring Ð transmitter timing see FigureRclk or Pxtalin DrvrTxen Ethernet timing of clock signalsEthernet timing of Xmit signals TXDRXD Ethernet timing of RCV signals Ð start of frameCRS RXC322 Ethernet timing of RCV signals Ð end of frameCrshld 320 321Norxc Ethernet timing of RCV signals Ð no RXCTXD Txen JAM 350TXC TXD Data80x8x DIO read timing Sdben SCS, SrsxSRS0± SRS2 Sbhe Sras80x8x DIO write timing 282W 283W 276 279 275 282b Valid 264 265 268 256267 272a 280 281 281a287 First 286 Second 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse SRD, SWR SCS SiackSADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High Sdben SRDY²HI-ZSWR Sown 80x8x mode bus arbitration timing, SIF takes controlSown SRD SWRSRD, SWR Sbbsy ShldaSADL0±SADL7 SPH, SPL High TwSCKL ± After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² This cycle 208bSbclk Sras Slds 80x8x mode DMA write timingSddir High SRD HighSADL0±SADH7 SADH0±SADL7 SPH, SPL80x8x mode bus arbitration timing, SIF returns control 208c 80x8x mode bus release timingSbrls Sown TW or68xxx DIO read timing SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SRS0, SRS1Siack Srnw Suds SldsSuds Slds Sdtack 68xxx DIO write timingSADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SDTACK²Siack Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack SCS Srnw Sdtack275 282a 255 SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPLSbrq 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High SbgrSADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL Sberr Sdtack SbbsySAS, Slds Suds SrnwSuds SAS 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low On this cycle 208bSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlWrite Read Sbclk Sbgr SdtackRead HI-Z Write SIF HI-ZSberr Sdtack 68xxx mode bus release and error timingSown Sberr Sbrls SownTH B TH E Sbclk Sdtack Sberr Shalt Sown Rerun cycle with delayed start²Normal completion with delayed start² Sbclk Sdtack Sberr ShaltMO±069±AD Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec NO. Outline Terminals MIN MAXImportant Notice