Texas Instruments TMS380C26 This cycle 208b, Delay from Sbclk low to address valid 214 ², 225R

Page 69
80x8x mode DMA read timing

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

NO.

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

205

Setup of SADL0±SADL7, SADH0±SADH7, SPH, and SPL valid before SBCLK in T3 cycle no

15

 

ns

longer high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

206

Hold of SADL0±SADL7, SADH0±SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if

15

 

ns

parameters 207a and 207b not met

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

207a

Hold of SADL0±SADL7, SADH0±SADH7, SPH, and SPL valid after

 

high

0

 

ns

SRD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

207b

Hold of SADL0±SADL7, SADH0±SADH7, SPH, and SPL valid after

 

 

no longer low

0

 

ns

SDBEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup of asynchronous signal

 

 

 

 

before SBCLK no longer high to guarantee recognition on

 

 

 

208a

SRDY

15

 

ns

this cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

208b

Hold of asynchronous signal

 

 

 

 

after SBCLK low to guarantee recognition on this cycle

15

 

ns

SRDY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

212

Delay from SBCLK low to address valid

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

214²

Delay from SBCLK low in T1 cycle to SADH0±SADH7, SADL0±SADL7, SPH, and SPL high-im-

 

25

ns

pedance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

215

Pulse duration, SALE and SXAL high

tc(SCK) ± 25

 

ns

216

Delay from SBCLK high to SALE or SXAL high

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

216a

Hold of SALE or SXAL low after

 

 

 

 

 

high

tw(SCKL) ± 15

 

ns

SRD

 

 

217

Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

218

Hold of SADH0±SADH7, SADL0±SADL7, SPH, and SPL valid after SALE or SXAL low

tw(SCKH) ± 15

 

ns

223R

Delay from SBCLK low in T4 cycle to

 

 

high (see Note 23)

 

25

ns

SRD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

225R

Delay from SBCLK low in T4 cycle to

 

 

 

high

 

25

ns

SDBEN

 

226²

Delay from SADH0±SADH7, SADL0±SADL7, SPH, and SPL high-impedance to

 

low

0

 

ns

SRD

 

227R

Delay from SBCLK low in T2 cycle to

 

 

low

 

25

ns

SRD

 

229²

Hold of SADH0±SADH7, SADL0±SADL7, SPH, and SPL high-impedance after SBCLK low in

0

 

ns

T1 cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

231

Pulse duration,

SRD

low

2tc(SCK) ± 30

 

ns

233

Setup of SADH0±SADH7, SADL0±SADL7, SPH, and SPL valid before SALE, SXAL no longer

tw(SCKL) ± 15

 

ns

high

 

 

 

 

 

 

 

 

 

 

 

 

237R

Delay from SBCLK high in the T2 cyle to

 

 

 

low

 

25

ns

SDBEN

 

 

 

 

 

 

247

Setup of data valid before

 

 

 

 

low if parameter 208a not met

0

 

ns

SRDY

 

²This specification has been characterized to meet stated value.

NOTE 23: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.

POST OFFICE BOX 1443 •HOUSTON, TEXAS

69

77251±1443

 

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Contents Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions TMS380C26 Terminal FunctionsPIN Name Description AX1 AX0 MaxphMaxpl AX3 AX2Mreset OUT SresetMOE MrasNSELOUT0 NSELOUT1 PrtyenSbhe = HSddir Direction DIO DMA ShrqSintr SWR SRD= Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode SyncinSystem Interface ± Motorola Mode SI/M = LSBHE/ Srnw Sbgr Terminal Functions = LSbrq SirqSuds SdtackSlds Nsrt FRAQ/TXDPxtalin RCVR/RXDLpbk TXCColl Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6Architecture Communications processor CPSystem interface SIF Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte TransfersBit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl RegisterBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP CodeBit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt ResultSysteminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See NoteHigh Low Test measurementVload IOL Output Under TestReference Periods WhenClkdiv = Oscout MBCLK1² MBCLK2² Timing parameter symbology Static signalsSignal Function Timing parametersParameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration HighMinimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 lowMreset MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph MaxplMADH0±MADH7 Memory bus timing clocks, MRAS, MCAS, and MAL to Address MADL0±MADL7 Maxph MaxplMromen MAL Address Column RowAddress Status Column StatusMcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph MaxplMras Mcas MAX0 MAX2 MromenAddress Status Data/Parity MbiaenMemory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas MbenParameter MIN Memory bus timing TMS380C26 releases control of busMBCLK1 MBCLK2 Mben 75a 74aMddir MAL Mbiaen Mbrq Mbgr Setup time High before MBCLK1 rising edge, bus resume Memory bus timing TMS380C26 resumes control of busHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Memory bus timing external bus master read from TMS380C26 MacsHold time Low after MBCLK2 low, external bus master read MBCLK1 MBCLK2 MAX0 MAX2 Maxph Maxpl MADH0±MADH7Mddir Macs Memory bus timing external bus master write to TMS380C26 MAX0, MAX2 Maxph MaxplData/Pty MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas MrefBit Xmatch and Xfail timing127 128 Xmatch XfailParameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk RcvrRclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD TxenCRS Ethernet timing of RCV signals Ð start of frameRXC RXDCrshld Ethernet timing of RCV signals Ð end of frame320 321 322Ethernet timing of RCV signals Ð no RXC NorxcTXD Txen TXC TXD 350Data JAM80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 SecondSddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR SownSbbsy Shlda SRD, SWRSADL0±SADL7 SPH, SPL 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ±Sbclk Sras Slds 80x8x mode DMA write timingSADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSuds Slds Sdtack 68xxx DIO write timingSDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack SdtackSdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr SbrqSAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlRead HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write ReadSown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr SdtackNormal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±ADImportant Notice
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