Texas Instruments TMS320DM643 manual Memory Map, Clock Configuration, PLLC2 Configuration

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Peripheral Architecture

2.1.2Clock Configuration

The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1 shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in Table 1 is derived by assuming a 27-MHZ reference clock. See the device-specific data manual for the clock frequencies that are supported. See the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978) for information on the PLL controller.

Note: PLLC2 should be configured and a stable clock present on PLL2_SYSCLK1 before releasing the DDR2 memory controller from reset.

Table 1. PLLC2 Configuration

PLL Multiplier	PLL Frequency (MHZ)	Divider Ratio	X2_CLK Frequency (MHZ)	DDR2 Clock Frequency (MHZ)
28	756	3	252	126
19	513	2	256.6	128.3
29	783	3	261	130.5
20	540	2	270	135
31	837	3	279	139.5
21	567	2	283.5	141.8
32	864	3	288	144
22	594	2	297	148.5
23	621	2	310	155.3
24	648	2	324	162
25	675	2	337.5	168.8

2.1.3DDR2 Memory Controller Internal Clock Domains

There are two clock domains within the DDR2 memory controller. The two clock domains are driven by VCLK and a divided-down by 2 version of X2_CLK called MCLK. The command FIFO, write FIFO, and read FIFO described in Section 2.8 are all on the VCLK domain. From this, you can see that VCLK drives the interface to the peripheral bus.

The MCLK domain consists of the DDR2 memory controller state machine and memory-mapped registers. This clock domain is clocked at the rate of the external DDR2 memory, X2_CLK/2.

To conserve power within the DDR2 memory controller, VCLK, MCLK, and X2_CLK may be stopped. See Section 2.16 for proper clock stop procedures.

2.2Memory Map

See the device-specific data manual for information describing the device memory-map.

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DDR2 Memory Controller

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesInternal Data 64-Bit DDRA21 DDRD150 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA2 DDRD310Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D63-32Acronym Register Description Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions DDR VTP RegisterSdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice