Texas Instruments TMS320DM643 manual Interrupt Support, DMA Event Support, Power Management

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Peripheral Architecture

2.14 Interrupt Support

The DDR2 memory controller supports two addressing modes, linear incrementing and cache line wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2 memory controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2 memory controller will then treat the request as a linear incrementing request.

This interrupt is called the line trap interrupt and is the only interrupt the DDR2 memory controller supports. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register (IMSR). This interrupt is mapped to both the DSP and the ARM and is not multiplexed with other interrupts.

2.15 DMA Event Support

The DDR2 memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data read and write requests may be made directly by masters and by the DMA.

2.16 Power Management

Power dissipation from the DDR2 memory controller may be managed by two methods:

∙Self-refresh mode (see Section 2.10)

∙Gating input clocks to the module off

Gating input clocks off to the DDR2 memory controller achieves higher power savings when compared to the power savings of self-refresh mode. The input clocks are turned off outside of the DDR2 memory controller through the use of the Power and Sleep Controller (PSC) and the PLL controller 2 (PLLC2). Figure 16 shows the connections between the DDR2 memory controller, PSC, and PLLC2. For detailed information on power management procedures using the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).

Before gating clocks off, the DDR2 memory controller must place the DDR2 SDRAM memory in self-refresh mode by setting the SR bit in the SDRAM refresh control register (SDRCR) to 1. If the external memory requires a continuous clock, the DDR2 memory controller clock provided by PLLC2 must not be turned off because this may result in data corruption. See the following subsections for the proper procedures to follow when stopping the DDR2 memory controller clocks. Once the clocks are stopped, to re-enable the clocks follow the clock stop procedure in each respective subsection in reverse order.

Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram

CLKSTOP_REQ

CLKSTOP_ACK

 

 

DDR

SYSCLK2

 

PSC

 

 

MODCLK

MODRST

LRST

PLLC2

/2

VCLKSTOP_REQ

VCLKSTOP_ACK

DDR2

memory

VCLK controller

VRST

VCTL_RST

X2_CLK

PLL2_SYSCLK1

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DDR2 Memory Controller

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesInternal Data 64-Bit DDRA21 DDRD150 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA2 DDRD310Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D63-32Acronym Register Description Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions DDR VTP RegisterSdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice
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