Texas Instruments TMS320DM643 manual List of Figures

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	List of Figures
1	Data Paths to DDR2 Memory Controller	8
2	DDR2 Memory Controller Clock Block Diagram	9
3	DDR2 Memory Controller Signals	11
4	Refresh Command	13
5	DCAB Command	14
6	DEAC Command	15
7	ACTV Command	16
8	DDR2 READ Command	17
9	DDR2 WRT Command	18
10	DDR2 MRS and EMRS Command	19
11	Byte Alignment	20
12	Logical Address-to-DDR2 SDRAM Address Map	24
13	DDR2 SDRAM Column, Row, and Bank Access	25
14	DDR2 Memory Controller FIFO Block Diagram	26
15	DDR2 Memory Controller Reset Block Diagram	30
16	DDR2 Memory Controller Power Sleep Controller Diagram	34
17	Connecting DDR2 Memory Controller for 32-Bit Connection	37
18	Connecting DDR2 Memory Controller for 16-Bit Connection	37
19	SDRAM Status Register (SDRSTAT)	41
20	SDRAM Bank Configuration Register (SDBCR)	42
21	SDRAM Refresh Control Register (SDRCR)	44
22	SDRAM Timing Register (SDTIMR)	45
23	SDRAM Timing Register 2 (SDTIMR2)	46
24	Peripheral Bus Burst Priority Register (PBBPR)	47
25	Interrupt Raw Register (IRR)	48
26	Interrupt Masked Register (IMR)	49
27	Interrupt Mask Set Register (IMSR)	50
28	Interrupt Mask Clear Register (IMCR)	51
29	DDR PHY Control Register (DDRPHYCR)	52
30	VTP IO Control Register (VTPIOCR)	53
31	DDR VTP Register (DDRVTPR)	54
32	DDR VTP Enable Register (DDRVTPER)	54

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List of Figures

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock SourceClock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsSignal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Considerations Bit External MemoryInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionSelf-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceDDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D63-32Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsAcronym Register Description DDR VTP RegisterSdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice