Texas Instruments TMS320DM643 manual Configuring Sdram Bank Configuration Register Sdbcr

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Supported Use Cases

3.2.1Configuring SDRAM Bank Configuration Register (SDBCR)

The SDRAM bank configuration register (SDBCR) contains register fields that configure the DDR2 memory controller to match the data bus width, CAS latency, number of banks, and page size of the attached DDR2 memory. In this example, we assume the following configuration:

∙Data bus width = 32 bits

∙CAS latency = 4

∙Number of banks = 8

∙Page size = 1024 words

Table 16 shows the resulting SDBCR configuration. Note that the value of the TIMUNLOCK bit is dependent on whether or not it is desirable to unlock SDTIMR and SDTIMR2. The TIMUNLOCK bit should only be set to 1 when the SDTIMR and SDTIMR2 needs to be updated.

Table 16. SDRAM Bank Configuration Register (SDBCR) Configuration

Field

Value

Function Selection

TIMUNLOCK

x

Set to 1 to unlock the SDRAM timing register (SDTIMR) and the SDRAM timing register 2

 

 

(SDTIMR2). Cleared to 0 to lock SDTIMR and SDTIMR2.

NM

0h

To configure the DDR2 memory controller for a 32-bit data bus width.

CL

4h

To select a CAS latency of 4.

IBANK

3h

To select 8 internal DDR2 banks.

PAGESIZE

2h

To select 1024-word page size.

3.2.2Configuring SDRAM Refresh Control Register (SDRCR)

The SDRAM refresh control register (SDRCR) configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device. SDRCR also allows the DDR2 memory controller to enter and exit self refresh and enable and disable the MCLK stopping. In this example, we assume that the DDR2 memory controller is not is in self-refresh mode and that MCLK stopping is disabled.

The RR bit field in SDRCR is defined as the rate at which the attached DDR2 device is refreshed in DDR2 cycles. The value of this field may be calculated using the following equation:

RR = DDR2 clock frequency × DDR2 refresh rate

Table 17 displays the DDR2-400 refresh rate specification.

Table 17. DDR2 Memory Refresh Specification

Symbol

Description

Value

tREF

Average Periodic Refresh Interval

7.8 μs

Therefore, the following assumes a 133-MHZ DDR2 clock frequency:

RR= 133 MHZ × 7.8 μs = 1037.4 Therefore, RR = 1038 = 40Eh.

Table 18 shows the resulting SDRCR configuration.

Table 18. SDRAM Refresh Control Register (SDRCR) Configuration

 

Field

Value

Function Selection

 

SR

0

DDR2 memory controller is not in self-refresh mode.

 

MCLKSTOPEN

0

MCLK stopping is disabled.

 

RR

40Eh

Set to 40Eh DDR2 clock cycles to meet the DDR2 memory refresh rate requirement.

38

DDR2 Memory Controller

 

SPRU986B–November 2007

 

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesInternal Data 64-Bit DDRA21 DDRD150 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA2 DDRD310Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D63-32Acronym Register Description Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions DDR VTP RegisterBit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice
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