Texas Instruments TMS320DM643 manual Supported Use Cases

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Supported Use Cases

3Supported Use Cases

The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. The programmability inherent to the DDR2 memory controller provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM bank configuration register (SDBCR), SDRAM refresh control register (SDRCR), SDRAM timing register (SDTIMR), and SDRAM timing register 2 (SDTIMR2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2 SDRAM.

This section presents an example describing how to interface the DDR2 memory controller to a JESD79D DDR2-400 1-Gb device. The DDR2 memory controller is assumed to be operating at 133 MHZ.

3.1Connecting the DDR2 Memory Controller to DDR2 Memory

The following figures show how to connect the DDR2 memory controller to a DDR2 device. Figure 17 displays a 32-bit interface; therefore, two 16-bit DDR2 devices are connected to the DDR2 memory controller. From Figure 17, you can see that the data bus, data strobe, and data mask (byte enable) signals are point-to-point where as all other address, control, and clocks are not. Figure 18 displays a

16-bit interface; therefore, all signals are point-to-point. See the device-specific data manual for the data bus widths that are supported.

3.2Configuring Memory-Mapped Registers to Meet DDR2-400 Specification

As previously stated, four memory-mapped registers must be programmed to configure the DDR2 memory controller to meet the data sheet specification of the attached DDR2 device. The registers are:

∙SDRAM bank configuration register (SDBCR)

∙SDRAM refresh control register (SDRCR)

∙SDRAM timing register (SDTIMR)

∙SDRAM timing register 2 (SDTIMR2)

In addition to these registers, the DDR PHY control register (DDRPHYCR) must also be programmed. The configuration of DDRPHYCR is not dependent on the DDR2 device specification but rather on the board layout.

The following sections describe how to configure each of these registers. See Section 4 for more information on the DDR2 memory controller registers.

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DDR2 Memory Controller

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock SourceClock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsSignal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Considerations Bit External MemoryInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionSelf-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceDDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D63-32Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsAcronym Register Description DDR VTP RegisterSdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice
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