Texas Instruments TMS320DM643 manual Sdram Timing Register Sdtimr

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DDR2 Memory Controller Registers

4.4SDRAM Timing Register (SDTIMR)

The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. The SDTIMR register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2 memory data sheet for information on the appropriate values to program each field. The SDTIMR is shown in Figure 22 and described in Table 28.

Figure 22. SDRAM Timing Register (SDTIMR)

31

 

 

25

24

22

21

19

18

 

16

 

T_RFC

 

 

 

T_RP

 

T_RCD

 

T_WR

 

 

R/W-1Ah

 

 

 

R/W-5h

 

R/W-5h

 

R/W-3h

 

15

11

10

 

 

6

5

3

2

1

0

 

T_RAS

 

 

T_RC

 

 

T_RRD

Rsvd

T_WTR

 

R/W-9h

 

 

R/W-Eh

 

 

R/W-3h

R-0

R/W-3h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 28. SDRAM Timing Register (SDTIMR) Field Descriptions

Bit

Field

Value

Description

31-25

T_RFC

0-7Fh

Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh

 

 

 

or activate command, minus 1. Corresponds to the trfc AC timing parameter in the DDR2 data sheet.

 

 

 

Calculate by:

 

 

 

T_RFC = (trfc/DDR_CLK period) - 1

24-22

T_RP

0-7h

Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate

 

 

 

command, minus 1. Corresponds to the trp AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RP = (trp/DDR_CLK period) - 1

21-19

T_RCD

0-7h

Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write

 

 

 

command, minus 1. Corresponds to the trcd AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RCD = (trcd/DDR_CLK period) - 1

18-16

T_WR

0-7h

Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge

 

 

 

command, minus 1. Corresponds to the twr AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_WR = (twr/DDR_CLK period) - 1

 

 

 

When the value of this field is changed from its previous value, the initialization sequence will begin.

15-11

T_RAS

0-1Fh

Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge

 

 

 

command, minus 1. Corresponds to the tras AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RAS = (tras/DDR_CLK period) - 1

 

 

 

T_RAS must be greater than or equal to T_RCD.

10-6

T_RC

0-1Fh

Specifies the minimum number of DDR_CLK cycles from an activate command to an activate

 

 

 

command, minus 1. Corresponds to the trc AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RC = (trc/DDR_CLK period) - 1

5-3

T_RRD

0-7h

Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command

 

 

 

in a different bank, minus 1. Corresponds to the trrd AC timing parameter in the DDR2 data sheet.

 

 

 

Calculate by:

 

 

 

T_RRD = (trrd/DDR_CLK period) - 1

 

 

 

Note: for an 8 bank DDR2 device this field must be equal to ((4 × tRRD) + (2 × tCK)) / (4 × tCK) - 1.

2

Reserved

0

Reserved

1-0

T_WTR

0-3h

Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.

 

 

 

Corresponds to the twtr AC timing parameter in the DDR2 data sheet. Calculate by:

T_WTR = (twtr/DDR_CLK period) - 1

SPRU986B–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness ConsiderationsInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D63-32Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatAcronym Register Description DDR VTP RegisterSdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice
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