Texas Instruments TMS320DM643 manual Sdram Status Register Sdrstat, Acronym Register Description

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DDR2 Memory Controller Registers

Table 22. DDR2 Memory Controller Registers Relative to Base Address 2000 0000h

Offset	Acronym	Register Description	Section
4h	SDRSTAT	SDRAM Status Register	Section 4.1
8h	SDBCR	SDRAM Bank Configuration Register	Section 4.2
Ch	SDRCR	SDRAM Refresh Control Register	Section 4.3
10h	SDTIMR	SDRAM Timing Register	Section 4.4
14h	SDTIMR2	SDRAM Timing Register 2	Section 4.5
20h	PBBPR	Peripheral Bus Burst Priority Register	Section 4.6
C0h	IRR	Interrupt Raw Register	Section 4.7
C4h	IMR	Interrupt Masked Register	Section 4.8
C8h	IMSR	Interrupt Mask Set Register	Section 4.9
CCh	IMCR	Interrupt Mask Clear Register	Section 4.10
E4h	DDRPHYCR	DDR PHY Control Register	Section 4.11
F0h	VTPIOCR	VTP IO Control Register	Section 4.12

Table 23. DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h

Offset	Acronym	Register Description	Section
38h	DDRVTPR	DDR VTP Register	Section 4.13

Table 24. DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h

Offset	Acronym	Register Description	Section
4Ch	DDRVTPER	DDR VTP Enable Register	Section 4.14

4.1SDRAM Status Register (SDRSTAT)

The SDRAM status register (SDRSTAT) is shown in Figure 19 and described in Table 25.

Figure 19. SDRAM Status Register (SDRSTAT)

31				16
	Reserved
	R-4000h
15	3	2	1	0
Reserved		PHYRDY	Reserved
R-0		R-0		R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset; -x = value is indeterminate after reset

Table 25. SDRAM Status Register (SDRSTAT) Field Descriptions

Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2	PHYRDY		DDR2 memory controller DLL ready. Reflects whether the DDR2 memory controller DLL is powered up
			and locked.
		0	DLL is not ready, either powered down, in reset, or not locked.
		1	DLL is powered up, locked, and ready for operation.
1-0	Reserved	0	Reserved

SPRU986B–November 2007	DDR2 Memory Controller	41
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness ConsiderationsInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D63-32Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatAcronym Register Description DDR VTP RegisterBit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice