Texas Instruments TMS320DM643 manual Clock Control, Clock Source

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Peripheral Architecture

2Peripheral Architecture

This section describes the architecture of the DDR2 memory controller as well as how it is structured and how it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. The following sections include details on how to interface and properly configure the DDR2 memory controller to perform read and write operations to externally-connected DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device.

2.1Clock Control

The DDR2 memory controller receives two input clocks from internal clock sources, SYSCLK2 and PLL2_SYSCLK1 (Figure 2). SYSCLK2 is a divided-down version of the DSP clock. PLL2_SYSCLK1 should be configured to clock at the frequency of the desired data rate, or stated similarly, it should operate at twice the frequency of the desired DDR2 memory clock. DDR_CLK and DDR_CLK are the two output clocks of the DDR2 memory controller providing the interface clock to the DDR2 SDRAM memory. These two clocks operate at a frequency of PLL2_SYSCLK1/2.

2.1.1Clock Source

SYSCLK2 and PLL2_SYSCLK1 are sourced from two independent PLLs (Figure 2). SYSCLK2 is sourced from PLL controller 1 (PLLC1) and PLL2_SYSCLK1 is sourced from PLL controller 2 (PLLC2).

SYSCLK2 is clocked at a fixed divider ratio of PLL1. This divider is fixed at 3, meaning SYSCLK2 is clocked at a frequency of PLL1/3. Once inside the DDR2 memory controller, this signal is called VCLK.

PLLC2 has a programmable divider that is used to divide-down the output clock of PLL2. This divider should be configured such that PLLC2 supplies the PLL2_SYSCLK1 at the desired frequency. For example, if a 150-MHZ DDR2 interface clock (DDR_CLK) is desired, then PLLC2 must be configured to generate a 300-MHZ clock on PLL2_SYSCLK1. Once inside the DDR2 memory controller, PLL2_SYSCLK1 is called X2_CLK.

Figure 2. DDR2 Memory Controller Clock Block Diagram

DDR_CLK DDR_CLK

DDR2 memory controller

VCLKX2_CLK

PLL2_SYSCLK1

/2

PLLC2

SYSCLK2

/3

PLLC1

SPRU986B–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness ConsiderationsInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D63-32Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatAcronym Register Description DDR VTP RegisterSdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice
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