Texas Instruments TMS320DM643 Reset Considerations, Reset Sources, Reset Signal Reset Source

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Peripheral Architecture

Once in self-refresh mode, the DDR2 memory controller input clocks (VCLK and X2_CLK) may be gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See Section 2.16 for more information describing the proper procedure to follow when shutting down DDR2 memory controller input clocks.

2.11 Reset Considerations

The DDR2 memory controller has two reset signals, VRST and VCTL_RST. The VRST is a module-level reset that resets both the state machine as well as the DDR2 memory controller memory-mapped registers. The VCTL_RST resets the state machine only. If the DDR2 memory controller is reset independently of other peripherals, the user's software should not perform memory, as well as register accesses, while VRST or VCTL_RST are asserted. If memory or register accesses are performed while the DDR2 memory controller is in the reset state, other masters may hang. Following the rising edge of VRST or VCTL_RST, the DDR2 memory controller immediately begins its initialization sequence. Command and data stored in the DDR2 memory controller FIFOs are lost. Table 13 describes the different methods for asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978). Figure 15 shows the DDR2 memory controller reset diagram.

	Table 13. Reset Sources
Reset Signal	Reset Source
VRST	Hardware/device reset
VCTL_RST	Power and sleep controller

Figure 15. DDR2 Memory Controller Reset Block Diagram

Hard

Reset from

PLLC1

DDR

PSC

VRST

VCTL_RST

DDR2

memory controller registers

State

machine

30

DDR2 Memory Controller

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesInternal Data 64-Bit DDRA21 DDRD150 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA2 DDRD310Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D63-32Acronym Register Description Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions DDR VTP RegisterSdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice