Texas Instruments TMS320DM643 manual Peripheral Architecture

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Peripheral Architecture

2.13.2Initializing Following Device Power Up and Device RESET

CAUTION

The following power-up sequence is preliminary and is documented to reflect the intended-use case. This power-up sequence may change at a future date.

Following device power up, the DDR2 memory controller is held in reset with the internal clocks to the module gated off. Before releasing the DDR2 memory controller from reset, the clocks to the module must be turned on. Perform the following steps when turning the clocks on and initializing the module:

1.Program PLLC2 registers to provide a stable clock on PLL2_SYSCLK1 at the desired frequency.

2.Program the DDR2 memory controller Power and Sleep Controller (PSC) to enable VCLK.

3.Follow the register initialization procedure described in Section 2.13.1 to complete the DDR2 memory controller configuration.

4.Perform a dummy read of DDR2 memory to verify initialization sequence has completed.

5.Perform a soft reset of the DDR2 memory controller via the PSC using the following procedure. See the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978) for details on how to program the PSC.

a.To put the DDR2 memory controller into soft reset, program the PSC to place the DDR2 memory controller into the SyncReset state.

b.To take the DDR2 memory controller out of soft reset, program the PSC to place the DDR2 memory controller into the Enable state.

6.Enable VTP manual calibration by writing to the VTP IO control register (VTPIOCR). See Section 4.12 for details on VTPIOCR.

a.With a single write, set the EN bit field (bit 13) to 1 and the RECAL bit field (bit 15) to 0 by writing a value of 0000 201Fh.

b.Set the RECAL bit field (bit 15) to 1, making sure the value written to the EN field is still 1 by writing a value of 0000 A01Fh. This begins the calibration sequence.

7.Wait for a minimum of 33 VTP clk cycles for calibration to complete. The VTP clock operates at 13.5 MHZ.

8.Enable access to the DDR VTP register by writing a 1 to the DDR VTP enable register.

9.Read the DDR VTP register to get the P/N channel VTP value. See Section 4.13 for details on the DDR VTP register.

10.Write the VTP information to the PCH and NCH fields in the VTPIOCR. Make sure the RECAL and EN bits remain set to 1.

11.Write 0 to EN bit field in the VTP control register to disable VTP calibration.

12.Disable access to the DDR VTP register by writing a 0 to the DDR VTP enable register.

13.Disable VTP input clock by disabling the bypass clock of PLL2.

Note: If the DDR2 memory controller is reset via the Power and Sleep Controller (PSC) and the VTP input clock is disabled, accesses to the DDR2 memory controller will not complete. To re-enable accesses to the DDR2 memory controller, enable the VTP input clock and then perform the VTP calibration sequence again.

SPRU986B–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness ConsiderationsInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D63-32Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatAcronym Register Description DDR VTP RegisterSdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice
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