Texas Instruments TMS320DM643 manual Mode Register Set MRS and Emrs, DDR2 MRS and Emrs Command

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Peripheral Architecture

2.4.6Mode Register Set (MRS and EMRS)

DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2 device), single-ended strobe, etc.

The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into the register. Figure 10 shows the timing for an MRS and EMRS command.

The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence. See Section 2.13 for more information.

Figure 10. DDR2 MRS and EMRS Command

MRS/EMRS

DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]	COL

DDR_BA[2:0] BANK

SPRU986B–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentInternal Data 64-Bit DDRA2 DDRD310 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA21 DDRD150Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Sources Reset ConsiderationsReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationD63-32 Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration Register Field Name DescriptionDDR VTP Register Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Acronym Register DescriptionSdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice