Texas Instruments TMS320DM643 manual Sdram Refresh Control Register Sdrcr

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DDR2 Memory Controller Registers

4.3SDRAM Refresh Control Register (SDRCR)

The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to:

∙Enter and Exit the self-refresh state.

∙Enable and disable MCLK, stopping when in the self-refresh state.

∙Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands.

The SDRCR is shown in Figure 21 and described in Table 27.

Figure 21. SDRAM Refresh Control Register (SDRCR)

31	30	29	24	23	22	16
SR	MCLKSTOPEN		Reserved	Rsvd		Reserved
R/W-0	R/W-0		R-0	R/W-0		R-0
15						0
			RR
			R/W-884h
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 27. SDRAM Refresh Control Register (SDRCR) Field Descriptions

Bit	Field	Value	Description
31	SR		Self refresh.
		0	DDR2 memory controller exits the self-refresh mode.
		1	DDR2 memory controller enters the self-refresh mode.
30	MCLKSTOPEN		MCLK stop enable.
		0	Disables MCLK stopping, MCLK may not be stopped.
		1	Enables MCLK stopping, MCLK may be stopped. The SR bit must be set to 1 before setting the
			MCLKSTOPEN bit to 1.
29-24	Reserved	0	Reserved
23	Reserved	0	Reserved. Always write 0 to this bit.
22-16	Reserved	0	Reserved
15-0	RR	0-FFFFh	Refresh rate. Defines the rate at which the attached DDR2 devices will be refreshed. The value

of this field may be calculated with the following equation:

RR = DDR2 clock frequency (in MHZ) × DDR2 refresh rate (in μs)

where DDR2 refresh rate is derived from the DDR2 data sheet. Writing a value < 0100h to this field causes it to be loaded with the value 2 × T_RFC from the SDRAM timing register (SDTIMR).

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DDR2 Memory Controller

SPRU986B–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Control Clock SourceClock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsSignal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Considerations Bit External MemoryInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionSelf-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources VTP IO Buffer Calibration Auto-Initialization SequenceDDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D63-32Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsAcronym Register Description DDR VTP RegisterBit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice