Texas Instruments TMS320 DSP manual Program Memory, Data Bss Object files Size

Page 40

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Program Memory

Algorithms must characterize their static data memory requirements by filling out a table such as that illustrated below. Each row represents the requirements for an individual object file that is part of the algorithm'simplementation. Each named COFF section (that contains data) in the algorithm'sobject files is represented by a column. Each entry should contain the size (in 8-bit bytes) required by the algorithm, any alignment requirements, whether the data is read-only or read-write, and whether the data is scratch memory or not. If no special alignment is required, the alignment number should be set to zero.

 

 

 

.data

 

 

 

.bss

 

Object files

Size

Align

Read/Write

Scratch

Size

Align

Read/Write

Scratch

a.obj

12

0

R

no

32

0

R

no

b.obj

0

0

R

no

0

0

R

no

Static data in an algorithm forces the system integrator to dedicate a region of the system'smemory to a single specific purpose. While this may be desirable in some systems, it is rarely the right decision for all systems. Moreover, modifiable static data usually indicates that the algorithm is not reentrant. Unless special precautions are taken, it is not possible for a reentrant function to modify static data.

Guideline 6

Algorithms should minimize their static memory requirements.

With the exception of initialized data, it is possible to virtually eliminate all static data in an algorithm using the eXpressDSP-compliant IALG interface. The implementation of interfaces is described in Section 3.2 and a detailed description of the IALG interface is provided in the TMS320 DSP Algorithm Standard API Reference.

Guideline 7

Algorithms should never have any scratch static memory.

4.2Program Memory

Algorithm code can often be partitioned into two distinct types: frequently accessed code and infrequently accessed code. Obviously, inner loops of algorithms are frequently accessed. However, like most application code, it is often the case that a few functions account for most of the MIPS required by an application.

Guideline 8

Algorithm code should be partitioned into distinct sections and each section should be characterized by the average number of instructions executed per input sample.

Characterizing the number of instructions per sample for each algorithm allows system integrators to optimally assign on-chip program memory to the appropriate algorithms. It also allows one to perform a quantitative cost/benefit analysis of simple on-chip program overlay policies, for example.

Rule 22

All algorithms must characterize their program memory requirements.

All algorithms must characterize their program memory requirements by filling out a table such as that shown below. Each entry should contain the size (in 8-bit bytes) required by the algorithm and any alignment requirements. If no special alignment is required, the alignment number should be set to zero

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Algorithm Performance Characterization

SPRU352G –June 2005 –Revised February 2007

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Contents Users Guide Rules and GuidelinesSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Related Documentation Text ConventionsRule n Guideline nOverview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6xRules and Guidelines Requirements of the StandardGoals of the Standard Intentional OmissionsSystem Architecture FrameworksAlgorithms Core Run-Time SupportGeneral Programming Guidelines Use of C Language Threads and ReentrancyThreads RulePreemptive vs. Non-Preemptive Multitasking ReentrancyExample Data Memory Data MemoryMemory Spaces Scratch versus PersistentScratch vs Persistent Memory Allocation Algorithm versus Application GuidelineROM-ability Program MemorySection Name Purpose Use of Peripherals Use of PeripheralsAlgorithm Component Model Interfaces and Modules Algorithms PackagingInterfaces and Modules Implementation Fir.hExternal Identifiers Module Initialization and Finalization Naming ConventionsModule Instance Objects Design-Time Object Creation Run-Time Object Creation and DeletionModule Configuration Example ModuleMultiple Interface Support Interface Inheritance SummaryElement Description RequiredAlgorithms AlgorithmsPackaging Object CodeHeader Files Debug Verses ReleaseModuleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution TimeExternal Heap MemorySize Stack Memory Static Local and Global Data MemoryData Bss Object files Size Interrupt Latency Execution TimeMips Is Not Enough OperationExecution Time Model Execution Timeline for Two Periodic Tasks198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register TypesUse of Floating Point TMS320C6xxx Rules and GuidelinesEndian Byte Ordering Data ModelsRegister Conventions Status RegisterRegister Use Type CSR Field Use TypeTMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Relocatability ExampleSSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy TMS320C24xx Guidelines GeneralTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer RequestsOverview Algorithm and FrameworkRequirements for the Use of the DMA Resource Logical ChannelData Transfer Properties Data Transfer SynchronizationDMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Runtime APIs Strong Ordering of DMA Transfer RequestsSubmitting DMA Transfer Requests Device Independent DMA Optimization GuidelineCache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and GuidelinesSupporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and GuidelinesMinimizing Logical Channel Reconfiguration Overhead Addressing Automatic Endianism Conversion IssuesInter-Algorithm Synchronization Non-Preemptive SystemPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIsDSP/BIOS Run-time Support Library TI C-Language Run-Time Support LibraryBibliography BooksSubmit Documentation Feedback Glossary Glossary of TermsGlossary of Terms Glossary of Terms Important Notice