Texas Instruments TMS320 DSP Status Registers, ST0 Field Name Use Type, ST1 Field Name Use Type

Page 51

www.ti.com

TMS320C54xx Rules and Guidelines

5.4.3 Register Conventions

This section describes the rules and guidelines that apply to the use of the TMS320C54xx on-chip registers. As described above, there are several different register types. Note that any register that is not described here must not be accessed by an algorithm; e.g., BSCR, IFR, IMR, and peripheral control and status registers.

The table below describes all of the registers that may be accessed by an algorithm

Register

Use

Type

AR0, AR2-AR5

C compiler expression registers

Scratch (local)

AR7

C compiler frame pointer

Preserve (local)

AR1, AR6

C compiler register variables

Preserve (local)

AL, AH, AG

Return value from C function, first parameter to function

Scratch (local)

BL, BH, BG

C compiler expression registers

Scratch (local)

BK

Circular-buffer size register

Scratch (local)

BRC

Block repeat counter

Scratch (local)

IFR, IMR

Interrupt flag and mask register

Read-only (global)

PMST

Processor mode register

Preserve

RSA, REA

Block repeat start and end register

Scratch (local)

SP

Stack pointer

Preserve (local)

ST0, ST1

Status registers

Preserve

T

Multiply and shift operand

Scratch (local)

TRN

Viterbi transition register

Scratch (local)

XPC

Extended Program Counter

Scratch (local)

5.4.4 Status Registers

The C54xx contains three status registers: ST0, ST1, and PMST. Each status register is further divided into several distinct fields. Although each field is often thought of as a separate register, it is not possible to access these fields individually. In order to set one field, it is necessary to set all fields in the same status register. Therefore, it is necessary to treat the status registers with special care. For example, if any field of a status register is of type Preserve, the entire register must be treated as a Preserve register.

ST0 Field Name

Use

Type

ARP

Auxiliary register pointer

Init (local)

C

Carry bit

Scratch (local)

DP

Data page pointer

Scratch (local)

OVA

Overflow flag for accumulator A

Scratch (local)

OVB

Overflow flag for accumulator B

Scratch (local)

TC

Test/Control flag

Scratch (local)

The ST1 register is of type Init.

ST1 Field Name

Use

Type

 

ASM

Accumulator shift mode

Scratch (local)

 

BRAF

Block repeat active bit

Preserve (local)

 

C16

Dual 16-bit math bit

Init (local)

 

CMPT

Compatibility mode bit

Init (local)

 

CPL

Compiler mode bit

Init (local)

 

FRCT

Fractional mode bit

Init (local)

 

HM

Hold mode bit

Preserve (local)

 

SPRU352G –June 2005 –Revised February 2007

DSP-Specific Guidelines

51

Submit Documentation Feedback

 

 

 

Page 50 Page 52
Image 51
Page 50 Page 52
Contents Rules and Guidelines Users GuideSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Read This First Intended AudienceDocument Overview Guideline n Related DocumentationText Conventions Rule nOverview Rules for TMS320C5x Rules for TMS320C6x Scope of the StandardRequirements of the Standard Rules and GuidelinesIntentional Omissions Goals of the StandardFrameworks System ArchitectureCore Run-Time Support AlgorithmsGeneral Programming Guidelines Rule Use of C LanguageThreads and Reentrancy ThreadsReentrancy Preemptive vs. Non-Preemptive MultitaskingExample Data Memory Data MemoryScratch versus Persistent Memory SpacesScratch vs Persistent Memory Allocation Guideline Algorithm versus ApplicationProgram Memory ROM-abilitySection Name Purpose Use of Peripherals Use of PeripheralsInterfaces and Modules Algorithms Packaging Algorithm Component ModelImplementation Fir.h Interfaces and ModulesExternal Identifiers Naming Conventions Module Initialization and FinalizationModule Instance Objects Run-Time Object Creation and Deletion Design-Time Object CreationExample Module Module ConfigurationMultiple Interface Support Description Required Interface InheritanceSummary ElementAlgorithms AlgorithmsObject Code PackagingDebug Verses Release Header FilesModuleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance CharacterizationHeap Memory ExternalSize Static Local and Global Data Memory Stack MemoryData Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not EnoughExecution Timeline for Two Periodic Tasks Execution Time ModelProcess 19800059000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register TypesData Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte OrderingCSR Field Use Type Register ConventionsStatus Register Register Use TypeInterrupt Latency TMS320C54xx Rules and GuidelinesProgram Models TMS320C54xx Rules and Guidelines Status Registers ST0 Field Name Use TypeST1 Field Name Use Type TMS320C55x Rules and Guidelines Stack ArchitecturePmst Field Name Use Type Example RelocatabilitySSP Status Bits ST2 Field Name Use TypeST3 Field Name Use Type Homy General TMS320C24xx GuidelinesTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA ResourceAlgorithm and Framework OverviewLogical Channel Requirements for the Use of the DMA ResourceData Transfer Synchronization Data Transfer PropertiesAbstract Interface DMA GuidelineDMA Rule Resource Characterization Data Transfers bytes FrequencyAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIsDevice Independent DMA Optimization Guideline Submitting DMA Transfer Requests13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA TransfersNon-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm SynchronizationPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support LibraryTI C-Language Run-Time Support Library DSP/BIOS Run-time Support LibraryBooks BibliographySubmit Documentation Feedback Glossary of Terms GlossaryGlossary of Terms Glossary of Terms Important Notice
Top Page Image Contents