Texas Instruments TMS320 DSP manual Performance Characterization Rules, DMA Rules

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Performance Characterization Rules

Rule 25 — All C6x algorithms must be supplied in little-endian format. (See Section 5.3.1)

Rule 26 — All C6x algorithms must access all static and global data as far data. (See Section 5.3.2)

Rule 27 — C6x algorithms must never assume placement in on-chip program memory; i.e., they must properly operate with program memory operated in cache mode. (See Section 5.3.3)

Rule 28 — On processors that support large program model compilation, all function accesses to independently relocatable object modules must be far references. For example, intersection function references within algorithm and external function references to other eXpressDSP-compliant modules must be far on the C54x; i.e., the calling function must push both the XPC and the current PC. (See Section 5.4.2)

Rule 29 — On processors that support large program model compilation, all independently relocatable object module functions must be declared as far functions; for example, on the C54x, callers must push both the XPC and the current PC and the algorithm functions must perform a far return. (See Section 5.4.2)

Rule 30 — On processors that support an extended program address space (paged memory), the code size of any independently relocatable object module should never exceed the code space available on a page when overlays are enabled. (See Section 5.4.2)

Rule 31 — All C55x algorithms must document the content of the stack configuration register that they follow. (See Section 5.5.1)

Rule 32 — All C55x algorithms must access all static and global data as far data; also the algorithms should be instantiable in a large memory model. (See Section 5.5.2)

Rule 33 — C55x algorithms must never assume placement in on-chip program memory; i.e., they must properly operate with program memory operated in instruction cache mode. (See Section 5.5.3)

Rule 34 — All C55x algorithms that access data by B-bus must document: the instance number of the IALG_MemRec structure that is accessed by the B-bus (heap-data), and the data-section name that is accessed by the B-bus (static-data). (See Section 5.5.4)

Rule 35 — All TMX320C28x algorithms must access all static and global data as far data; also, the algorithm should be instantiable in a large memory model. (See Section 5.7.1)

A.2 Performance Characterization Rules

Rule 19 — All algorithms must characterize their worst-case heap data memory requirements (including alignment). (See Section 4.1.1)

Rule 20 — All algorithms must characterize their worst-case stack space memory requirements (including alignment). (See Section 4.1.2)

Rule 21 — Algorithms must characterize their static data memory requirements. (See Section 4.1.3) Rule 22 — All algorithms must characterize their program memory requirements. (See Section 4.2)

Rule 23 — All algorithms must characterize their worst-case interrupt latency for every operation. (See Section 4.3)

Rule 24 — All algorithms must characterize the typical period and worst-case execution time for each operation. (See Section 4.4.2)

A.3 DMA Rules

DMA Rule 1 — All data transfer must be completed before return to caller. (See Section 6.6)

DMA Rule 2 — All algorithms using the DMA resource must implement the IDMA2 interface. (See Section 6.7)

SPRU352G –June 2005 –Revised February 2007

Rules and Guidelines

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Contents Rules and Guidelines Users GuideSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Document Overview Read This FirstIntended Audience Text Conventions Related DocumentationRule n Guideline nOverview Rules for TMS320C5x Rules for TMS320C6x Scope of the StandardRequirements of the Standard Rules and GuidelinesIntentional Omissions Goals of the StandardFrameworks System ArchitectureCore Run-Time Support AlgorithmsGeneral Programming Guidelines Threads and Reentrancy Use of C LanguageThreads RuleReentrancy Preemptive vs. Non-Preemptive MultitaskingExample Data Memory Data MemoryScratch versus Persistent Memory SpacesScratch vs Persistent Memory Allocation Guideline Algorithm versus ApplicationSection Name Purpose Program MemoryROM-ability Use of Peripherals Use of PeripheralsInterfaces and Modules Algorithms Packaging Algorithm Component ModelImplementation Fir.h Interfaces and ModulesExternal Identifiers Module Instance Objects Naming ConventionsModule Initialization and Finalization Run-Time Object Creation and Deletion Design-Time Object CreationExample Module Module ConfigurationMultiple Interface Support Summary Interface InheritanceElement Description RequiredAlgorithms AlgorithmsObject Code PackagingDebug Verses Release Header FilesModuleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance CharacterizationSize Heap MemoryExternal Static Local and Global Data Memory Stack MemoryData Bss Object files Size Execution Time Interrupt LatencyMips Is Not Enough OperationExecution Timeline for Two Periodic Tasks Execution Time Model59000 198000 Process198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register TypesTMS320C6xxx Rules and Guidelines Use of Floating PointEndian Byte Ordering Data ModelsStatus Register Register ConventionsRegister Use Type CSR Field Use TypeProgram Models Interrupt LatencyTMS320C54xx Rules and Guidelines TMS320C54xx Rules and Guidelines ST1 Field Name Use Type Status RegistersST0 Field Name Use Type Pmst Field Name Use Type TMS320C55x Rules and GuidelinesStack Architecture Example RelocatabilitySSP ST3 Field Name Use Type Status BitsST2 Field Name Use Type Homy General TMS320C24xx GuidelinesTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA ResourceAlgorithm and Framework OverviewLogical Channel Requirements for the Use of the DMA ResourceData Transfer Synchronization Data Transfer PropertiesDMA Rule Abstract InterfaceDMA Guideline Average Maximum Resource CharacterizationData Transfers bytes Frequency Strong Ordering of DMA Transfer Requests Runtime APIsDevice Independent DMA Optimization Guideline Submitting DMA Transfer Requests13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA TransfersAddressing Automatic Endianism Conversion Issues Minimizing Logical Channel Reconfiguration OverheadInter-Algorithm Synchronization Non-Preemptive SystemPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support LibraryTI C-Language Run-Time Support Library DSP/BIOS Run-time Support LibraryBooks BibliographySubmit Documentation Feedback Glossary of Terms GlossaryGlossary of Terms Glossary of Terms Important Notice
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