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6.14.2 Minimizing Logical Channel Reconfiguration Overhead
Some common C55x DMA devices impose additional restrictions that affect when a channel needs to be reconfigured. A logical channel needs to be reconfigured when the source or destination addresses refer to different memory ports (SARAM, DARAM, EMIF) compared with the most recently configured channel settings.
Additionally, utilizing the reload registers is not possible when the source or destination addresses correspond to different memory ports currently being used by the ongoing transfer.
DMA Guideline 5
C55x algorithms should minimize channel configuration overhead by requesting a separate logical channel for each different transfer type. They should also call ACPY2_configure when the source or destination addresses belong in a different type of memory (SARAM, DARAM, External) as compared with that of the most recent transfer.
6.14.3Addressing Automatic Endianism Conversion Issues
Some C55x/OMAP architectures perform
DMA Rule 10
C55x algorithms must request all data buffers in external memory with
DMA Rule 11
C55x algorithms must use the same data types, access modes and DMA transfer settings when reading from or writing to data stored in external memory, or in
6.15 Inter-Algorithm Synchronization
An ideal system with unlimited DMA resources would assign a physical DMA channel to each logical channel requested by the algorithms comprising the system. Unfortunately, the DMA resource is limited and some of the physical DMA channels may be used for other system functions such as servicing serial ports etc. As such, a variety of application scenarios are possible with regards to sharing physical DMA channels. Let'sconsider two scenarios to illustrate how this can be dealt with: a
6.15.1Non-Preemptive System
Assume a system with one physical DMA channel that has been assigned to be used by two algorithms. The algorithms require one logical channel each. The algorithms do not preempt each other.
We know from DMA Rule 1 that upon return from the algorithm functions, the DMA is not active. The system can easily share this single DMA channel among the two algorithms, since they will run sequentially and use the DMA channel sequentially. See Section 6.15.2.
SPRU352G | Use of the DMA Resource | 71 |