Texas Instruments TMS320 DSP manual General Rules

Page 76

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General Rules

Recall that rules must be followed in order for software to be eXpressDSP-compliant. Guidelines, on the other hand, are strongly suggested guidelines that should be obeyed but may be violated by eXpressDSP-compliant software.

The rules are partitioned into three distinct sections. The first two sections enumerate all of the rules and guidelines that must be obeyed by the algorithms and the third section gathers all performance characterization rules.

A.1 General Rules

Rule 1 — All algorithms must follow the run-time conventions imposed by TI'simplementation of the C programming language. (See Section 2.1)

Rule 2 — All algorithms must be reentrant within a preemptive environment (including time-sliced preemption). (See Section 2.2.3)

Rule 3 — All algorithm data references must be fully relocatable (subject to alignment requirements). That is, there must be no "hard coded" data memory locations. (See Section 2.3.1)

Rule 4 — All algorithm code must be fully relocatable. That is, there can be no hard coded program memory locations. (See Section 2.4)

Rule 5 — Algorithms must characterize their ROM-ability; i.e., state whether they are ROM-able or not. (See Section 2.5)

Rule 6 — Algorithms must never directly access any peripheral device. This includes but is not limited to on-chip DMAs, timers, I/O devices, and cache control registers. Note, however, algorithms can utilize the DMA resource by implementing the IDMA2 interface. (See Section 2.6)

Rule 7 — All header files must support multiple inclusions within a single source file. (See Section 3.1)

Rule 8 — All external definitions must be either API identifiers or API and vendor prefixed. (See Section 3.1.1)

Rule 9 — All undefined references must refer either to the operations specified in Appendix B (a subset of C runtime support library functions and a subset of the DSP/BIOS HWI API functions) or TI's DSPLIB or IMGLIB functions, or other eXpressDSP-compliant modules. (See Section 3.1.1)

Rule 10 — All modules must follow the eXpressDSP-compliant naming conventions for those external declarations disclosed to the client. (See Section 3.1.2)

Rule 11 — All modules must supply an initialization and finalization method. (See Section 3.1.3) Rule 12 — All algorithms must implement the IALG interface. (See Section 3.2)

Rule 13 — Each of the IALG methods implemented by an algorithm must be independently relocatable. (See Section 3.2)

Rule 14 — All abstract algorithm interfaces must derive from the IALG interface. (See Section 3.2)

Rule 15 — Each eXpressDSP-compliant algorithm must be packaged in an archive which has a name that follows a uniform naming convention. (See Section 3.3.1)

Rule 16 — Each eXpressDSP-compliant algorithm header must follow a uniform naming convention. (See Section 3.3.2)

Rule 17 — Different versions of an eXpressDSP-compliant algorithm from the same vendor must follow a uniform naming convention. (See Section 3.3.3)

Rule 18 — If a module'sheader includes definitions specific to a "debug" variant, it must use the symbol _DEBUG to select the appropriate definitions; _DEBUG is defined for debug compilations and only for debug compilations. (See Section 3.3.3)

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Rules and Guidelines

SPRU352G –June 2005 –Revised February 2007

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Contents Users Guide Rules and GuidelinesSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Related Documentation Text ConventionsRule n Guideline nOverview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6xRules and Guidelines Requirements of the StandardGoals of the Standard Intentional OmissionsSystem Architecture FrameworksAlgorithms Core Run-Time SupportGeneral Programming Guidelines Use of C Language Threads and ReentrancyThreads RulePreemptive vs. Non-Preemptive Multitasking ReentrancyExample Data Memory Data MemoryMemory Spaces Scratch versus PersistentScratch vs Persistent Memory Allocation Algorithm versus Application GuidelineROM-ability Program MemorySection Name Purpose Use of Peripherals Use of PeripheralsAlgorithm Component Model Interfaces and Modules Algorithms PackagingInterfaces and Modules Implementation Fir.hExternal Identifiers Module Initialization and Finalization Naming ConventionsModule Instance Objects Design-Time Object Creation Run-Time Object Creation and DeletionModule Configuration Example ModuleMultiple Interface Support Interface Inheritance SummaryElement Description RequiredAlgorithms AlgorithmsPackaging Object CodeHeader Files Debug Verses ReleaseModuleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution TimeExternal Heap MemorySize Stack Memory Static Local and Global Data MemoryData Bss Object files Size Interrupt Latency Execution TimeMips Is Not Enough OperationExecution Time Model Execution Timeline for Two Periodic Tasks198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register TypesUse of Floating Point TMS320C6xxx Rules and GuidelinesEndian Byte Ordering Data ModelsRegister Conventions Status RegisterRegister Use Type CSR Field Use TypeTMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Relocatability ExampleSSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy TMS320C24xx Guidelines GeneralTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer RequestsOverview Algorithm and FrameworkRequirements for the Use of the DMA Resource Logical ChannelData Transfer Properties Data Transfer SynchronizationDMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Runtime APIs Strong Ordering of DMA Transfer RequestsSubmitting DMA Transfer Requests Device Independent DMA Optimization GuidelineCache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and GuidelinesSupporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and GuidelinesMinimizing Logical Channel Reconfiguration Overhead Addressing Automatic Endianism Conversion IssuesInter-Algorithm Synchronization Non-Preemptive SystemPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIsDSP/BIOS Run-time Support Library TI C-Language Run-Time Support LibraryBibliography BooksSubmit Documentation Feedback Glossary Glossary of TermsGlossary of Terms Glossary of Terms Important Notice
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