Texas Instruments TMS320 DSP manual Multiple Interface Support

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Interfaces and Modules

typedef

struct FIR_Obj { /*

FIR_Obj definition

*/

int

hist[16];

/*

previous input value */

int

frameLen;

/* input frame length

*/

int

*coeff;

 

 

 

} FIR_Obj;

FIR_Handle FIR_create(FIR_Obj *fir, const FIR_Params *params)

{

if (fir != NULL) {

if (params == NULL) { /* use defaults if params is NULL */ params = &FIR_PARAMS;

}

fir->frameLen = params->frameLen; fir->coeff = params->coeff; memset(fir->hist, 0, sizeof (fir->hist));

}

return (fir);

}

The delete entry point should release any resource held by the object being deleted and should gracefully handle the deletion of partially constructed objects; the delete entry point may be called by the create operation. In this case, there is nothing to do.

void FIR_delete(FIR_Handle fir)

{

}

Finally, the FIR module must provide a method for filtering a signal. This is accomplished via the apply operation shown below.

void FIR_apply(FIR_Handle fir, int in[], int out[])

{

int I;

/* filter data using coefficients fir->coeff and history fir->hist */

for (I = 0; I < fir->frameLen; I++) {

out[i] = filter(in[i], fir->coeff, fir->hist);

}

}

Of course, in a real FIR module, the filter operation would be implemented in assembly language. However, because the state necessary to compute the algorithm is entirely contained in the object pointed to by fir, this algorithm is reentrant. Thus, it is easy to use this module in multichannel applications or in single-channel applications which require more than one FIR filter.

3.1.9 Multiple Interface Support

Modern component programming models support the ability of a single component to implement more than one interface. This allows a single component to be used concurrently by a variety of different applications. For example, in addition to a component'sconcrete interface (defined by its header) a component might also support a debug interface that allows debuggers to inquire about the existence and extent of the component'sdebug capabilities. If all debuggable components implement a common abstract debug interface, debuggers can be written that can uniformly debug arbitrary components.

Support for multiple interfaces is generally incorporated into the development environment (via Code wizards), the programming language itself, or both. Since this standard is intended to only require the C language, the ability of a module to support multiple interfaces is at best awkward.

However, several significant benefits make this approach worthwhile:

a vendor may decide not to implement certain interfaces for some components,

new interfaces can be defined without affecting existing components,

multiple implementations of the same interface may be present in a single system, and

partitioning a large interface into multiple simpler interfaces makes it easier to understand the component as a whole.

As stated before, interfaces are defined by header files; each header defines a single interface. A

SPRU352G –June 2005 –Revised February 2007

Algorithm Component Model

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Contents Rules and Guidelines Users GuideSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Guideline n Related DocumentationText Conventions Rule nOverview Rules for TMS320C5x Rules for TMS320C6x Scope of the StandardRequirements of the Standard Rules and GuidelinesIntentional Omissions Goals of the StandardFrameworks System ArchitectureCore Run-Time Support AlgorithmsGeneral Programming Guidelines Rule Use of C LanguageThreads and Reentrancy ThreadsReentrancy Preemptive vs. Non-Preemptive MultitaskingExample Data Memory Data MemoryScratch versus Persistent Memory SpacesScratch vs Persistent Memory Allocation Guideline Algorithm versus ApplicationROM-ability Program MemorySection Name Purpose Use of Peripherals Use of PeripheralsInterfaces and Modules Algorithms Packaging Algorithm Component ModelImplementation Fir.h Interfaces and ModulesExternal Identifiers Module Initialization and Finalization Naming Conventions Module Instance Objects Run-Time Object Creation and Deletion Design-Time Object CreationExample Module Module ConfigurationMultiple Interface Support Description Required Interface InheritanceSummary ElementAlgorithms AlgorithmsObject Code PackagingDebug Verses Release Header FilesModuleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance CharacterizationExternal Heap MemorySize Static Local and Global Data Memory Stack MemoryData Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not EnoughExecution Timeline for Two Periodic Tasks Execution Time Model198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register TypesData Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte OrderingCSR Field Use Type Register ConventionsStatus Register Register Use TypeTMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Example RelocatabilitySSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy General TMS320C24xx GuidelinesTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA ResourceAlgorithm and Framework OverviewLogical Channel Requirements for the Use of the DMA ResourceData Transfer Synchronization Data Transfer PropertiesDMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIsDevice Independent DMA Optimization Guideline Submitting DMA Transfer Requests13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA TransfersNon-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm SynchronizationPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support LibraryTI C-Language Run-Time Support Library DSP/BIOS Run-time Support LibraryBooks BibliographySubmit Documentation Feedback Glossary of Terms GlossaryGlossary of Terms Glossary of Terms Important Notice