Texas Instruments
TMS320 DSP
manual
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Module Configuration
Page 44
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44
Algorithm Performance Characterization
SPRU352G
–June
2005
–Revised
February 2007
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Page 43
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Contents
Users Guide
Rules and Guidelines
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Contents
Use of the DMA Resource
Urls
List of Figures
Document Overview
Read This First
Intended Audience
Related Documentation
Text Conventions
Rule n
Guideline n
Overview
Scope of the Standard
Rules for TMS320C5x Rules for TMS320C6x
Rules and Guidelines
Requirements of the Standard
Goals of the Standard
Intentional Omissions
System Architecture
Frameworks
Algorithms
Core Run-Time Support
General Programming Guidelines
Use of C Language
Threads and Reentrancy
Threads
Rule
Preemptive vs. Non-Preemptive Multitasking
Reentrancy
Example
Data Memory
Data Memory
Memory Spaces
Scratch versus Persistent
Scratch vs Persistent Memory Allocation
Algorithm versus Application
Guideline
Section Name Purpose
Program Memory
ROM-ability
Use of Peripherals
Use of Peripherals
Algorithm Component Model
Interfaces and Modules Algorithms Packaging
Interfaces and Modules
Implementation Fir.h
External Identifiers
Module Instance Objects
Naming Conventions
Module Initialization and Finalization
Design-Time Object Creation
Run-Time Object Creation and Deletion
Module Configuration
Example Module
Multiple Interface Support
Interface Inheritance
Summary
Element
Description Required
Algorithms
Algorithms
Packaging
Object Code
Header Files
Debug Verses Release
Moduleversvendorvariant.1arch
Algorithm Performance Characterization
Data Memory Program Memory Interrupt Latency Execution Time
Size
Heap Memory
External
Stack Memory
Static Local and Global Data Memory
Data Bss Object files Size
Interrupt Latency
Execution Time
Mips Is Not Enough
Operation
Execution Time Model
Execution Timeline for Two Periodic Tasks
59000 198000
Process
198000
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DSP-Specific Guidelines
CPU Register Types
Register Types
Use of Floating Point
TMS320C6xxx Rules and Guidelines
Endian Byte Ordering
Data Models
Register Conventions
Status Register
Register Use Type
CSR Field Use Type
Program Models
Interrupt Latency
TMS320C54xx Rules and Guidelines
TMS320C54xx Rules and Guidelines
ST1 Field Name Use Type
Status Registers
ST0 Field Name Use Type
Pmst Field Name Use Type
TMS320C55x Rules and Guidelines
Stack Architecture
Relocatability
Example
SSP
ST3 Field Name Use Type
Status Bits
ST2 Field Name Use Type
Homy
TMS320C24xx Guidelines
General
TMS320C28x Rules and Guidelines
TMS320C28x Rules and Guidelines
XAR0
M0M1MAP
Use of the DMA Resource
Submitting DMA Transfer Requests
Overview
Algorithm and Framework
Requirements for the Use of the DMA Resource
Logical Channel
Data Transfer Properties
Data Transfer Synchronization
DMA Rule
Abstract Interface
DMA Guideline
Average Maximum
Resource Characterization
Data Transfers bytes Frequency
Runtime APIs
Strong Ordering of DMA Transfer Requests
Submitting DMA Transfer Requests
Device Independent DMA Optimization Guideline
Cache Coherency Issues for Algorithm Producers
13 C6xxx Specific DMA Rules and Guidelines
Supporting Packed/Burst Mode DMA Transfers
14 C55x Specific DMA Rules and Guidelines
Minimizing Logical Channel Reconfiguration Overhead
Addressing Automatic Endianism Conversion Issues
Inter-Algorithm Synchronization
Non-Preemptive System
Preemptive System
Algorithm B Algorithm a
Inter-Algorithm Synchronization
Appendix a
General Rules
Performance Characterization Rules
DMA Rules
General Guidelines
DMA Guidelines
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DSP/BIOS Run-time Support Library
Core Run-Time APIs
DSP/BIOS Run-time Support Library
TI C-Language Run-Time Support Library
Bibliography
Books
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Glossary
Glossary of Terms
Glossary of Terms
Glossary of Terms
Important Notice
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