www.ti.com
C6xxx Specific DMA Rules and Guidelines
6.13 C6xxx Specific DMA Rules and Guidelines
6.13.1 Cache Coherency Issues for Algorithm Producers
In certain C6000 targets, data that are in both external memory and the L2 cache can cause coherence problems with background DMA transfers in several ways. The figures below depict some memory access scenarios that potentially lead to problems. We later introduce rules and guidelines for both algorithm and framework developers to ensure correct operation of C6000 algorithms.
In Section 6.13.2, CPU access of the memory corresponding to location x brings it into the L2 cache. Subsequent writes to x take place in the L2 cache until the cache line containing x gets written back to external memory. If a DMA transfer starts copying the data from location x to another location, it may end up reading stale value of x in external memory since certain DMA controllers will not detect presence or flushing of a dirty cache line containing x. To avoid this problem, the cache must be flushed before the DMA read proceeds.
X = 0ld Y = new
Y
L2 cache
X | X |
External memory | DMA |
In Section 6.13.3, the location x has been brought into the L2 cache. Suppose a DMA transfer writes new data to location x. In this case, the CPU would access the old cached data in a subsequent read, unless the cached copy is invalidated.
X = 0ld Y = new
Y
L2 cache
X | Y |
External memory | DMA |
|
Algorithms must enforce coherence and alignment/size constraints for internal buffers they request through the IALG interface. To deal with these coherency problems, the following new guidelines and rules have been added.
DMA Guideline 3
To ensure correctness, All C6000 algorithms that implement IDMA2 need to be supplied with the internal memory they request from the client application using algAlloc().
This guideline applies to the client application, rather than to the algorithm. If DMA Guideline 3 is followed; i.e., if the type of memory requested is provided, the algorithm is guaranteed to operate correctly.
DMA Rule 6
C6000 algorithms must not issue any CPU read/writes to buffers in external memory that are involved in DMA transfers. This also applies to buffers passed to the algorithm through its algorithm interface.
DMA Rule 6 is necessary because it is the only way for an
DMA Rule 7
If a C6000 algorithm has implemented the IDMA2 interface, the client must allocate all the required external memory at a cache line boundary. These buffers must be a multiple of cache line length in size. The client must also ensure that these buffers are not in cache before passing them to the algorithm.
SPRU352G | Use of the DMA Resource | 69 |