Texas Instruments TMS320 DSP manual Ssp

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TMS320C55x Rules and Guidelines

If the algorithm does not use B-bus, then the first column must be zero. If there is more than one block that is accessed by the B-bus, then all the block numbers must be specified in the second column as shown in the above example.

Example 2:

Any static-data that is accessed by the B-bus must be documented as per the Rule 37 as follows:

Data section names that are accessed by the

B-bus

.data

.coefwords

This way, the client will know which of the memory blocks and data-sections must be placed in on-chip memory for the correct execution of the algorithm.

5.5.5 Register Conventions

This section describes the rules and guidelines that apply to the use of the TMS320C55x on-chip registers. Note that an algorithm must not access any register that is not described here.

The table below describes all of the registers that may be accessed by an algorithm. Please refer to TMS320C55x Optimizing C/C++ Compiler User's Guide (SPRU281), Runtime Environment chapter, for more details about the runtime conventions followed by the compiler.

 

Register

Use

Type

 

(X)AR0, (X)AR1, (X)AR2, (X)AR3, (X)AR4

Function arguments: data pointers (16- or 23-bit) or

Scratch (local)

 

 

data values (16-bit)

 

 

(X)AR5, (X)AR6, (X)AR7

C compiler register variables

Preserve (local)

 

AC0, AC1, AC2, AC3

16-bit, 32-bit and 40-bit data or 24-bit code pointers

Scratch (local)

 

T0, T1

Function arguments: 16-bit data values

Scratch (local)

 

T2, T3

C compiler expression registers

Preserve (local)

 

SSP

System Stack Pointer

Preserve (local)

 

SP

Stack Pointer

Preserve (local)

 

ST0, ST1, ST2, ST3

Status registers

Preserve (local)

 

IFR0, IMR0, IFR1, IMR1

Interrupt flag and mask register

Read-only (global)

 

TRN0, TRN1

Transition registers

Scratch (local)

 

BK03, BK47, BKC

Circular Buffer Offset registers

Scratch (local)

 

BRC0, BRC1

Block Repeat Counter registers

Scratch (local)

 

RSA0, REA0, RSA1, REA1

Block repeat start and end address registers

Scratch (local)

 

CDP

Coefficient Data Pointer

Scratch (local)

 

XDP

Extended Data page pointer

Scratch (local)

 

DP

Memory data page start address

Scratch (local)

 

PDP

Peripheral Data page start address

Scratch (local)

 

BOF01, BOF23, BOF45, BOF67, BOFC

Circular buffer offset registers

Scratch (local)

 

BIOS

Data page pointer storage

Read-only (global)

 

BRS0, BRS1

Block repeat save registers

Scratch (local)

 

CSR

Computed Single Repeat

Scratch (local)

 

RPTC

Repeat Single Counter

Scratch (local)

 

XSP

Extended data Stack pointer

Preserve (local)

 

XCDP

Extended coeff page pointer

Scratch (local)

 

IVPD

Interrupt vector pointer DSP

Read-only (global)

 

IVPH

Interrupt vector pointer host

Read-only (global)

54

DSP-Specific Guidelines

SPRU352G –June 2005 –Revised February 2007

 

 

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Contents Users Guide Rules and GuidelinesSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Read This First Intended AudienceDocument Overview Rule n Related DocumentationText Conventions Guideline nOverview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6xRules and Guidelines Requirements of the StandardGoals of the Standard Intentional OmissionsSystem Architecture FrameworksAlgorithms Core Run-Time SupportGeneral Programming Guidelines Threads Use of C LanguageThreads and Reentrancy RulePreemptive vs. Non-Preemptive Multitasking ReentrancyExample Data Memory Data MemoryMemory Spaces Scratch versus PersistentScratch vs Persistent Memory Allocation Algorithm versus Application GuidelineProgram Memory ROM-abilitySection Name Purpose Use of Peripherals Use of PeripheralsAlgorithm Component Model Interfaces and Modules Algorithms PackagingInterfaces and Modules Implementation Fir.hExternal Identifiers Naming Conventions Module Initialization and FinalizationModule Instance Objects Design-Time Object Creation Run-Time Object Creation and DeletionModule Configuration Example ModuleMultiple Interface Support Element Interface InheritanceSummary Description RequiredAlgorithms AlgorithmsPackaging Object CodeHeader Files Debug Verses ReleaseModuleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution TimeHeap Memory ExternalSize Stack Memory Static Local and Global Data MemoryData Bss Object files Size Mips Is Not Enough Interrupt LatencyExecution Time OperationExecution Time Model Execution Timeline for Two Periodic TasksProcess 19800059000 198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register TypesEndian Byte Ordering Use of Floating PointTMS320C6xxx Rules and Guidelines Data ModelsRegister Use Type Register ConventionsStatus Register CSR Field Use TypeInterrupt Latency TMS320C54xx Rules and GuidelinesProgram Models TMS320C54xx Rules and Guidelines Status Registers ST0 Field Name Use Type ST1 Field Name Use Type TMS320C55x Rules and Guidelines Stack ArchitecturePmst Field Name Use Type Relocatability ExampleSSP Status Bits ST2 Field Name Use TypeST3 Field Name Use Type Homy TMS320C24xx Guidelines GeneralTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer RequestsOverview Algorithm and FrameworkRequirements for the Use of the DMA Resource Logical ChannelData Transfer Properties Data Transfer SynchronizationAbstract Interface DMA GuidelineDMA Rule Resource Characterization Data Transfers bytes FrequencyAverage Maximum Runtime APIs Strong Ordering of DMA Transfer RequestsSubmitting DMA Transfer Requests Device Independent DMA Optimization GuidelineCache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and GuidelinesSupporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and GuidelinesInter-Algorithm Synchronization Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Non-Preemptive SystemPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIsDSP/BIOS Run-time Support Library TI C-Language Run-Time Support LibraryBibliography BooksSubmit Documentation Feedback Glossary Glossary of TermsGlossary of Terms Glossary of Terms Important Notice
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