Texas Instruments TMS320 DSP manual Resource Characterization, Data Transfers bytes Frequency

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Resource Characterization

DMA Rule 3

Each of the IDMA2 or IDMA3 methods implemented by an algorithm must be independently relocateable.

The pragma directive must be used to place each method in appropriate subsections to enable independent relocatability of the methods by the system integrator. The table below summarizes the section names and their purpose.

Section Name

Purpose

.text:dmaGetChannels

Implementation of the IDMA2 or IDMA3 dmaGetChannels method

.text:<name>

Implementation of the IDMA2 or IDMA3 <name> method

In other words, an algorithm'simplementation of the IDMA2 or IDMA3 method <name> should be placed in a COFF section named ".text:<name>".

6.8Resource Characterization

The resources consumed by algorithms implementing the IALG interface are restricted to MIPS and memory. These resources must be documented according to the rules defined in Chapter 4. Algorithms implementing the IDMA2 or IDMA3 interface will consume an additional system resource. This resource must also be documented.

Some DMA managers use software queuing for DMA jobs. These systems need to know how many DMA transfers are queued up so that it can set aside memory to hold the information for all the transfers. It is important that the system integrator knows the worst-case depth of the queue of DMA jobs (number of concurrent transfers) on each logical channel.

DMA Rule 4

All algorithms must state the maximum number of concurrent DMA transfers for each logical channel.

This can be accomplished by filling out a table such as that shown below.

Logical channel number

Number of concurrent transfers

 

(depth of queue)

0

3

1

1

In the example above, that algorithm requires two DMA logical channels; channel 0 will not issue more than three concurrent DMA transfers, and channel 1 will not issue more that one concurrent DMA transfer.

It is important that system integrators be able to wisely optimize the assignments of DMA resources among algorithms. For example, if a system integrator chooses to share a physical DMA channel between algorithms in a preemptive system, the frequency of the data transfers and the size of the data transfers might affect this assignment.

DMA Rule 5

All agorithms must characterize the average and maximum size of the data transfers per logical channel for each operation. Also, all algorithms must characterize the average and maximum frequency of data transfers per logical channel for each operation.

This can be accomplished by filling out a table such as that shown below.

 

Logical

Data Transfers (bytes)

Frequency

 

Channel

 

 

 

 

Operation

Number

Average

Maximum

Average

Maximum

algActivate()

0

512

512

1

1

process()

0

768

1024

5

7

process()

1

64

128

8

8

66

Use of the DMA Resource

SPRU352G –June 2005 –Revised February 2007

 

 

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Contents Users Guide Rules and GuidelinesSubmit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Read This First Intended AudienceDocument Overview Rule n Related DocumentationText Conventions Guideline nOverview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6xRules and Guidelines Requirements of the StandardGoals of the Standard Intentional OmissionsSystem Architecture FrameworksAlgorithms Core Run-Time SupportGeneral Programming Guidelines Threads Use of C LanguageThreads and Reentrancy RulePreemptive vs. Non-Preemptive Multitasking ReentrancyExample Data Memory Data MemoryMemory Spaces Scratch versus PersistentScratch vs Persistent Memory Allocation Algorithm versus Application GuidelineProgram Memory ROM-abilitySection Name Purpose Use of Peripherals Use of PeripheralsAlgorithm Component Model Interfaces and Modules Algorithms PackagingInterfaces and Modules Implementation Fir.hExternal Identifiers Naming Conventions Module Initialization and FinalizationModule Instance Objects Design-Time Object Creation Run-Time Object Creation and DeletionModule Configuration Example ModuleMultiple Interface Support Element Interface InheritanceSummary Description RequiredAlgorithms AlgorithmsPackaging Object CodeHeader Files Debug Verses ReleaseModuleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution TimeHeap Memory ExternalSize Stack Memory Static Local and Global Data MemoryData Bss Object files Size Mips Is Not Enough Interrupt LatencyExecution Time OperationExecution Time Model Execution Timeline for Two Periodic TasksProcess 19800059000 198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register TypesEndian Byte Ordering Use of Floating PointTMS320C6xxx Rules and Guidelines Data ModelsRegister Use Type Register ConventionsStatus Register CSR Field Use TypeInterrupt Latency TMS320C54xx Rules and GuidelinesProgram Models TMS320C54xx Rules and Guidelines Status Registers ST0 Field Name Use TypeST1 Field Name Use Type TMS320C55x Rules and Guidelines Stack ArchitecturePmst Field Name Use Type Relocatability ExampleSSP Status Bits ST2 Field Name Use TypeST3 Field Name Use Type Homy TMS320C24xx Guidelines GeneralTMS320C28x Rules and Guidelines TMS320C28x Rules and GuidelinesXAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer RequestsOverview Algorithm and FrameworkRequirements for the Use of the DMA Resource Logical ChannelData Transfer Properties Data Transfer SynchronizationAbstract Interface DMA GuidelineDMA Rule Resource Characterization Data Transfers bytes FrequencyAverage Maximum Runtime APIs Strong Ordering of DMA Transfer RequestsSubmitting DMA Transfer Requests Device Independent DMA Optimization GuidelineCache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and GuidelinesSupporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and GuidelinesInter-Algorithm Synchronization Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Non-Preemptive SystemPreemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA RulesGeneral Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIsDSP/BIOS Run-time Support Library TI C-Language Run-Time Support LibraryBibliography BooksSubmit Documentation Feedback Glossary Glossary of TermsGlossary of Terms Glossary of Terms Important Notice
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