Texas Instruments TMS320DM36X manual Read This First

Page 10

Preface

SPRUFI5B – March 2009 – Revised December 2010

Read This First

About This Manual

This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.

Notational Conventions

This document uses the following conventions.

•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

•Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the internet at www.ti.com.

SPRUFG5 — TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference

Guide This document describes the ARM Subsystem in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the components of the ARM Subsystem, the peripherals, and the external memories.

SPRUFG8 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End (VPFE) Users Guide This document describes the Video Processing Front End (VPFE) in the TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFG9 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE) Users Guide This document describes the Video Processing Back End (VPBE) in the TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFH0 — TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide This document describes the operation of the software-programmable64-bit timers in the TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFH1 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI) Users Guide This document describes the serial peripheral interface (SPI) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the DMSoC and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters.

10 PrefaceSPRUFI5B –March 2009 –Revised December 2010

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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramClock Control Industry Standards Compliance StatementMII Clocking Memory Map Signal DescriptionsMedia Independent Interface MII Connections Signal Type Description Emac and Mdio Signals for MII InterfacePin Multiplexing Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionPacket Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface WordBasic Descriptor Description Field Field DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber FlagBus Arbiter Emac Control ModuleInternal Memory CPUTransmit Pulse Interrupt Interrupt ControlReceive Pulse Interrupt Miscellaneous Pulse Interrupt Receive Threshold Pulse InterruptInterrupt Pacing Mdio Clock Generator Mdio ModuleMdio Module Components Global PHY Detection and Link State MonitoringActive PHY Monitoring PHY Register User AccessMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosReceive DMA Engine Emac ModuleEmac Module Components Receive FifoReceive Address Clock and Reset LogicMAC Receiver Transmit DMA EngineEmac Module Operational Overview Receive Control Media Independent Interface MIIData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address Matching Hardware Receive QOS SupportReceive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeReceive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization CodeEmac Module Initialization Receive Threshold Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Host Error Interrupt Statistics InterruptLink Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt ProcessingEmulation Control Power ManagementEmulation Considerations Soft Free DescriptionAcronym Register Description Emac Control Module RegistersSlave Vbus Bit Field Value DescriptionEmac Control Module Emulation Control Register Cmemcontrol Emac Control Module Software Reset Register CmsoftresetSoftreset Soft FreeIntpaceen Emac Control Module Interrupt Control Register CmintctrlIntprescale Rxthreshen RxpulseenTxpulseen Bit Field Statpendinten Hostpendinten Linkinten UserintenStatpendinten Rxthreshinttstat RxpulseinttstatTxpulseinttstat 31-8 Reserved TXPULSEINTTSTATnStatpendintstat Hostpendintstat Linkintstat Userintstat StatpendintstatRximax TximaxManagement Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident RxmajorverReceive Control Register Rxcontrol Field Descriptions Receive Control Register RxcontrolReceive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsTransmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorMAC End Of Interrupt Vector Register Maceoivector StatpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear HostmaskRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsLoopback TxflowenRxbufferflowen FullduplexMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsRxqosact Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions ValidMAC Index Register Macindex Field Descriptions MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register RxmcastframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register RxoversizedReceive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register RxfilteredGood Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Broadcast Transmit Frames Register TxbcastframesTransmit Collision Frames Register Txcollision Pause Transmit Frames Register TxpauseframesDeferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register TxsinglecollTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register RxdmaoverrunsAppendix a Glossary Physical Layer Definitions Term DefinitionDocument Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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