Texas Instruments TMS320DM36X manual Receive Packet Completion Interrupts

Page 56

Architecture

www.ti.com

Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding bit in the transmit interrupt mask set register (TXINTMASKSET) to 1. Each of the eight transmit channel interrupts may be individually disabled by clearing the corresponding bit in the transmit interrupt mask clear register (TXINTMASKCLEAR) to 0. The raw and masked transmit interrupt status may be read from the transmit interrupt status (unmasked) register (TXINTSTATRAW) and the transmit interrupt status (masked) register (TXINTSTATMASKED), respectively.

When the EMAC completes the transmission of a packet, the EMAC issues an interrupt to the CPU by writing the packet’s last buffer descriptor address to the appropriate channel queue’s transmit completion pointer located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt mask, regardless of the value written.

Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges an interrupt by writing the address of the last buffer descriptor processed to the queue’s associated transmit completion pointer in the transmit DMA state RAM.

The data written by the host (buffer descriptor address of the last processed buffer) is compared to the data in the register written by the EMAC port (address of last buffer descriptor used by the EMAC). If the two values are not equal (which means that the EMAC has transmitted more packets than the CPU has processed interrupts for), the transmit packet completion interrupt signal remains asserted. If the two values are equal (which means that the host has processed all packets that the EMAC has transferred), the pending interrupt is cleared. The value that the EMAC is expecting is found by reading the transmit channel n completion pointer register (TXnCP).

The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written value does not actually change the register value. The host written value is compared to the register content (which was written by the EMAC) and if the two values are equal then the interrupt is removed; otherwise, the interrupt remains asserted. The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet.

2.17.1.3Receive Packet Completion Interrupts

The receive DMA engine has eight channels, which each channel having a corresponding interrupt (RXPENDn). The receive interrupts are level interrupts that remain asserted until cleared by the CPU.

Each of the eight receive channel interrupts may be individually enabled by setting the corresponding bit in the receive interrupt mask set register (RXINTMASKSET) to 1. Each of the eight receive channel interrupts may be individually disabled by clearing the corresponding bit in the receive interrupt mask clear register (RXINTMASKCLEAR) to 0. The raw and masked receive interrupt status may be read from the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED), respectively.

When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the packet'slast buffer descriptor address to the appropriate channel queue'sreceive completion pointer located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt mask, regardless of the value written.

Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue'sassociated receive completion pointer in the receive DMA state RAM.

The data written by the host (buffer descriptor address of the last processed buffer) is compared to the data in the register written by the EMAC (address of last buffer descriptor used by the EMAC). If the two values are not equal (which means that the EMAC has received more packets than the CPU has processed interrupts for), the receive packet completion interrupt signal remains asserted. If the two values are equal (which means that the host has processed all packets that the EMAC has received), the pending interrupt is de-asserted. The value that the EMAC is expecting is found by reading the receive channel n completion pointer register (RXnCP).

The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written value does not actually change the register value. The host written value is compared to the register content (which was written by the EMAC) and if the two values are equal then the interrupt is removed; otherwise, the interrupt remains asserted. The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet.

56 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B –March 2009 –Revised December 2010

(MDIO)

Submit Documentation Feedback

 

© 2009–2010, Texas Instruments Incorporated

Page 55 Page 57
Image 56
Page 55 Page 57
Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramMII Clocking Industry Standards Compliance StatementClock Control Media Independent Interface MII Connections Signal DescriptionsMemory Map Pin Multiplexing Emac and Mdio Signals for MII InterfaceSignal Type Description Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors WordBasic Descriptor Description Field Field DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module Internal MemoryBus Arbiter CPUReceive Pulse Interrupt Interrupt ControlTransmit Pulse Interrupt Interrupt Pacing Receive Threshold Pulse InterruptMiscellaneous Pulse Interrupt Mdio Module Mdio Module ComponentsMdio Clock Generator Global PHY Detection and Link State MonitoringMdio Module Operational Overview PHY Register User AccessActive PHY Monitoring Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic MAC ReceiverReceive Address Transmit DMA EngineEmac Module Operational Overview Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address Matching Hardware Receive QOS SupportReceive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Receive Frame Treatment Promiscuous Receive ModeReceive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization CodeEmac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsReceive Threshold Interrupts Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Host Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Soft Free DescriptionEmac Control Module Registers Slave VbusAcronym Register Description Bit Field Value DescriptionEmac Control Module Software Reset Register Cmsoftreset SoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft FreeIntprescale Emac Control Module Interrupt Control Register CmintctrlIntpaceen Rxthreshen RxpulseenTxpulseen Statpendinten Statpendinten Hostpendinten Linkinten UserintenBit Field Rxthreshinttstat RxpulseinttstatTxpulseinttstat 31-8 Reserved TXPULSEINTTSTATnStatpendintstat Hostpendintstat Linkintstat Userintstat StatpendintstatRximax TximaxMdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Identification and Version Register Rxidver RxidentRxmajorver Rxminorver RxmajorverReceive Control Register Rxcontrol Receive Teardown Register RxteardownReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field DescriptionsTransmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC End Of Interrupt Vector Register MaceoivectorMAC Input Vector Register Macinvector Field Descriptions StatpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsTxflowen RxbufferflowenLoopback FullduplexMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsRxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 ValidMAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register TxsinglecollTransmit Underrun Error Register Txunderrun Transmit Carrier Sense Errors Register TxcarriersenseTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register RxdmaoverrunsAppendix a Glossary Physical Layer Definitions Term DefinitionDocument Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP
Related manuals
Manual 18 pages 38.41 Kb
Top Page Image Contents