Texas Instruments TMS320DM36X manual Emac Module Operational Overview

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Architecture

2.9.2EMAC Module Operational Overview

After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block. The transmit DMA controller then fetches the first packet in the packet chain from memory. The DMA controller writes the packet into the transmit FIFO in bursts of 64-byte cells. When the threshold number of cells, configurable using the TXCELLTHRESH bit in the FIFO control register (FIFOCONTROL), have been written to the transmit FIFO, or a complete packet, whichever is smaller, the MAC transmitter then initiates the packet transmission. The SYNC block transmits the packet over the MII interfaces in accordance with the 802.3 protocol. Transmit statistics are counted by the statistics block.

Receive operations are initiated by host writes to the appropriate receive channel head descriptor pointer after host initialization and configuration. The SYNC submodule receives packets and strips off the Ethernet related protocol. The packet data is input to the MAC receiver, which checks for address match and processes errors. Accepted packets are then written to the receive FIFO in bursts of 64-byte cells. The receive DMA controller then writes the packet data to memory. Receive statistics are counted by the statistics block.

The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is communicated by use of 16-byte descriptors that are placed in an 8K-byte block of RAM in the EMAC control module.

For transmit operations, each 16-byte descriptor describes a packet or packet fragment in the system's internal or external memory. For receive operations, each 16-byte descriptor represents a free packet buffer or buffer fragment. On both transmit and receive, an Ethernet packet is allowed to span one or more memory fragments, represented by one 16-byte descriptor per fragment. In typical operation, there is only one descriptor per receive buffer, but transmit packets may be fragmented, depending on the software architecture.

An interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it is not necessary for the CPU to service the interrupt while there are additional resources available. In other words, the EMAC continues to receive Ethernet packets until its receive descriptor list has been exhausted. On transmit operations, the transmit descriptors need only be serviced to recover their associated memory buffer. Thus, it is possible to delay servicing of the EMAC interrupt if there are real-time tasks to perform.

Eight channels are supplied for both transmit and receive operations. On transmit, the eight channels represent eight independent transmit queues. The EMAC can be configured to treat these channels as an equal priority "round-robin" queue or as a set of eight fixed-priority queues. On receive, the eight channels represent eight independent receive queues with packet classification. Packets are classified based on the destination MAC address. Each of the eight channels is assigned its own MAC address, enabling the EMAC module to act like eight virtual MAC adapters. Also, specific types of frames can be sent to specific channels. For example, multicast, broadcast, or other (promiscuous, error, etc.), can each be received on a specific receive channel queue.

The EMAC keeps track of 36 different statistics, plus keeps the status of each individual packet in its corresponding packet descriptor.

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 39

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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement Clock ControlMII Clocking Signal Descriptions Memory MapMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface Signal Type DescriptionPin Multiplexing Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame DescriptionWord Ethernet’s Multiple Access ProtocolProgramming Interface Packet Buffer DescriptorsField Field Description Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror FlagCPU Emac Control ModuleInternal Memory Bus ArbiterInterrupt Control Transmit Pulse InterruptReceive Pulse Interrupt Receive Threshold Pulse Interrupt Miscellaneous Pulse InterruptInterrupt Pacing Global PHY Detection and Link State Monitoring Mdio ModuleMdio Module Components Mdio Clock GeneratorPHY Register User Access Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeReceive Fifo Emac ModuleEmac Module Components Receive DMA EngineTransmit DMA Engine Clock and Reset LogicMAC Receiver Receive AddressEmac Module Operational Overview Receive Inter-Frame Interval Media Independent Interface MIIData Reception Receive ControlIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlInterpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APOSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Hardware Receive QOS Support Receive Address MatchingHost Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit LatencyReset Considerations Software Reset ConsiderationsTransfer Node Priority Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO PeripheralExample 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module InitializationEmac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Threshold InterruptsReceive Packet Completion Interrupts Statistics Interrupt Host Error InterruptProper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptSoft Free Description Power ManagementEmulation Considerations Emulation ControlBit Field Value Description Emac Control Module RegistersSlave Vbus Acronym Register DescriptionSoft Free Emac Control Module Software Reset Register CmsoftresetSoftreset Emac Control Module Emulation Control Register CmemcontrolEmac Control Module Interrupt Control Register Cmintctrl IntpaceenIntprescale Rxpulseen RxthreshenTxpulseen Statpendinten Hostpendinten Linkinten Userinten Bit FieldStatpendinten Rxpulseinttstat Rxthreshinttstat31-8 Reserved TXPULSEINTTSTATn TxpulseinttstatStatpendintstat Statpendintstat Hostpendintstat Linkintstat UserintstatTximax RximaxMdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Rxmajorver Receive Identification and Version Register RxidverRxident Rxmajorver RxminorverReceive Teardown Register Rxteardown Field Descriptions Receive Control Register RxcontrolReceive Teardown Register Rxteardown Receive Control Register Rxcontrol Field DescriptionsTX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearStatpend MAC Input Vector Register MacinvectorMAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register Macinvector Field DescriptionsRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask StatmaskRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolFullduplex TxflowenRxbufferflowen LoopbackMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusRxqosact Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field DescriptionsSoft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field DescriptionsValid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPMulticast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesFiltered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsBroadcast Transmit Frames Register Txbcastframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesTransmit Single Collision Frames Register Txsinglecoll Pause Transmit Frames Register TxpauseframesDeferred Transmit Frames Register Txdeferred Transmit Collision Frames Register TxcollisionTransmit Octet Frames Register Txoctets Transmit Underrun Error Register TxunderrunTransmit Carrier Sense Errors Register Txcarriersense Transmit Late Collision Frames Register TxlatecollSubmit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register NetoctetsAppendix a Glossary Term Definition Physical Layer DefinitionsReference Additions/Modifications/Deletions Document Revision HistoryProducts Applications DSPRfid
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