Texas Instruments TMS320DM36X manual Ethernet Media Access Controller Emac Registers

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Ethernet Media Access Controller (EMAC) Registers

5Ethernet Media Access Controller (EMAC) Registers

Table 37 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers.

Table 37. Ethernet Media Access Controller (EMAC) Registers

Offset	Acronym	Register Description	Section
0h	TXIDVER	Transmit Identification and Version Register	Section 5.1
4h	TXCONTROL	Transmit Control Register	Section 5.2
8h	TXTEARDOWN	Transmit Teardown Register	Section 5.3
10h	RXIDVER	Receive Identification and Version Register	Section 5.4
14h	RXCONTROL	Receive Control Register	Section 5.5
18h	RXTEARDOWN	Receive Teardown Register	Section 5.6
80h	TXINTSTATRAW	Transmit Interrupt Status (Unmasked) Register	Section 5.7
84h	TXINTSTATMASKED	Transmit Interrupt Status (Masked) Register	Section 5.8
88h	TXINTMASKSET	Transmit Interrupt Mask Set Register	Section 5.9
8Ch	TXINTMASKCLEAR	Transmit Interrupt Clear Register	Section 5.10
90h	MACINVECTOR	MAC Input Vector Register	Section 5.11
94h	MACEOIVECTOR	MAC End of Interrupt Vector Register	Section 5.12
A0h	RXINTSTATRAW	Receive Interrupt Status (Unmasked) Register	Section 5.13
A4h	RXINTSTATMASKED	Receive Interrupt Status (Masked) Register	Section 5.14
A8h	RXINTMASKSET	Receive Interrupt Mask Set Register	Section 5.15
ACh	RXINTMASKCLEAR	Receive Interrupt Mask Clear Register	Section 5.16
B0h	MACINTSTATRAW	MAC Interrupt Status (Unmasked) Register	Section 5.17
B4h	MACINTSTATMASKED	MAC Interrupt Status (Masked) Register	Section 5.18
B8h	MACINTMASKSET	MAC Interrupt Mask Set Register	Section 5.19
BCh	MACINTMASKCLEAR	MAC Interrupt Mask Clear Register	Section 5.20
100h	RXMBPENABLE	Receive Multicast/Broadcast/Promiscuous Channel Enable Register	Section 5.21
104h	RXUNICASTSET	Receive Unicast Enable Set Register	Section 5.22
108h	RXUNICASTCLEAR	Receive Unicast Clear Register	Section 5.23
10Ch	RXMAXLEN	Receive Maximum Length Register	Section 5.24
110h	RXBUFFEROFFSET	Receive Buffer Offset Register	Section 5.25
114h	RXFILTERLOWTHRESH	Receive Filter Low Priority Frame Threshold Register	Section 5.26
120h	RX0FLOWTHRESH	Receive Channel 0 Flow Control Threshold Register	Section 5.27
124h	RX1FLOWTHRESH	Receive Channel 1 Flow Control Threshold Register	Section 5.27
128h	RX2FLOWTHRESH	Receive Channel 2 Flow Control Threshold Register	Section 5.27
12Ch	RX3FLOWTHRESH	Receive Channel 3 Flow Control Threshold Register	Section 5.27
130h	RX4FLOWTHRESH	Receive Channel 4 Flow Control Threshold Register	Section 5.27
134h	RX5FLOWTHRESH	Receive Channel 5 Flow Control Threshold Register	Section 5.27
138h	RX6FLOWTHRESH	Receive Channel 6 Flow Control Threshold Register	Section 5.27
13Ch	RX7FLOWTHRESH	Receive Channel 7 Flow Control Threshold Register	Section 5.27
140h	RX0FREEBUFFER	Receive Channel 0 Free Buffer Count Register	Section 5.28
144h	RX1FREEBUFFER	Receive Channel 1 Free Buffer Count Register	Section 5.28
148h	RX2FREEBUFFER	Receive Channel 2 Free Buffer Count Register	Section 5.28
14Ch	RX3FREEBUFFER	Receive Channel 3 Free Buffer Count Register	Section 5.28
150h	RX4FREEBUFFER	Receive Channel 4 Free Buffer Count Register	Section 5.28
154h	RX5FREEBUFFER	Receive Channel 5 Free Buffer Count Register	Section 5.28
158h	RX6FREEBUFFER	Receive Channel 6 Free Buffer Count Register	Section 5.28
15Ch	RX7FREEBUFFER	Receive Channel 7 Free Buffer Count Register	Section 5.28
160h	MACCONTROL	MAC Control Register	Section 5.29

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 83

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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramMII Clocking Industry Standards Compliance StatementClock Control Media Independent Interface MII Connections Signal DescriptionsMemory Map Pin Multiplexing Emac and Mdio Signals for MII InterfaceSignal Type Description Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame DescriptionWord Ethernet’s Multiple Access ProtocolProgramming Interface Packet Buffer DescriptorsField Field Description Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror FlagCPU Emac Control ModuleInternal Memory Bus ArbiterReceive Pulse Interrupt Interrupt ControlTransmit Pulse Interrupt Interrupt Pacing Receive Threshold Pulse InterruptMiscellaneous Pulse Interrupt Global PHY Detection and Link State Monitoring Mdio ModuleMdio Module Components Mdio Clock GeneratorMdio Module Operational Overview PHY Register User AccessActive PHY Monitoring Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeReceive Fifo Emac ModuleEmac Module Components Receive DMA EngineTransmit DMA Engine Clock and Reset LogicMAC Receiver Receive AddressEmac Module Operational Overview Receive Inter-Frame Interval Media Independent Interface MIIData Reception Receive ControlIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlInterpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APOSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Hardware Receive QOS Support Receive Address MatchingReceive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Receive Frame Treatment Promiscuous Receive ModeReceive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit LatencyTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO PeripheralExample 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module InitializationEmac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Threshold InterruptsReceive Packet Completion Interrupts Statistics Interrupt Host Error InterruptProper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptSoft Free Description Power ManagementEmulation Considerations Emulation ControlBit Field Value Description Emac Control Module RegistersSlave Vbus Acronym Register DescriptionSoft Free Emac Control Module Software Reset Register CmsoftresetSoftreset Emac Control Module Emulation Control Register CmemcontrolIntprescale Emac Control Module Interrupt Control Register CmintctrlIntpaceen Rxpulseen RxthreshenTxpulseen Statpendinten Statpendinten Hostpendinten Linkinten UserintenBit Field Rxpulseinttstat Rxthreshinttstat31-8 Reserved TXPULSEINTTSTATn TxpulseinttstatStatpendintstat Statpendintstat Hostpendintstat Linkintstat UserintstatTximax RximaxMdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxmajorver Receive Identification and Version Register RxidverRxident Rxmajorver RxminorverReceive Teardown Register Rxteardown Field Descriptions Receive Control Register RxcontrolReceive Teardown Register Rxteardown Receive Control Register Rxcontrol Field DescriptionsTX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearStatpend MAC Input Vector Register MacinvectorMAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register Macinvector Field DescriptionsRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask StatmaskRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolFullduplex TxflowenRxbufferflowen LoopbackMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusRxqosact Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field DescriptionsSoft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field DescriptionsBack Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field DescriptionsValid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPMulticast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesFiltered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsBroadcast Transmit Frames Register Txbcastframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesTransmit Single Collision Frames Register Txsinglecoll Pause Transmit Frames Register TxpauseframesDeferred Transmit Frames Register Txdeferred Transmit Collision Frames Register TxcollisionTransmit Octet Frames Register Txoctets Transmit Underrun Error Register TxunderrunTransmit Carrier Sense Errors Register Txcarriersense Transmit Late Collision Frames Register TxlatecollSubmit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register NetoctetsAppendix a Glossary Term Definition Physical Layer DefinitionsReference Additions/Modifications/Deletions Document Revision HistoryRfid Products ApplicationsDSP

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