Texas Instruments TMS320DM36X manual Packet Transmit Operation, Receive and Transmit Latency

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Architecture

2.12 Packet Transmit Operation

The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7.

2.12.1Transmit DMA Host Configuration

To configure the transmit DMA for operation the host must perform:

•Write the MAC source address low bytes register (MACSRCADDRLO) and the MAC source address high bytes register (MACSRCADDRHI) (used for pause frames on transmit).

•Initialize the transmit channel n DMA head descriptor pointer registers (TXnHDP) to 0.

•Enable the desired transmit interrupts using the transmit interrupt mask set register (TXINTMASKSET) and the transmit interrupt mask clear register (TXINTMASKCLEAR).

•Set the appropriate configuration bits in the MAC control register (MACCONTROL).

•Setup the transmit channel(s) buffer descriptors in host memory.

•Enable the transmit DMA controller by setting the TXEN bit in the transmit control register (TXCONTROL).

•Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations.

2.12.2Transmit Channel Teardown

The host commands a transmit channel teardown by writing the channel number to the transmit teardown register (TXTEARDOWN). When a teardown command is issued to an enabled transmit channel, the following occurs:

•Any frame currently in transmission completes normally.

•The TDOWNCMPLT flag is set in the next SOP buffer descriptor in the chain, if there is one.

•The channel head descriptor pointer is cleared to 0.

•A transmit interrupt is issued to inform the host of the channel teardown.

•The corresponding transmit channel n completion pointer register (TXnCP) contains the value FFFF FFFCh.

•The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value.

Channel teardown may be commanded on any channel at any time. The host is informed of the teardown completion by the set teardown complete (TDOWNCMPLT) buffer descriptor bit. The EMAC does not clear any channel enables due to a teardown command. A teardown command to an inactive channel issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to TXnCP (note that there is no buffer descriptor in this case). Software may read the interrupt acknowledge location (TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command.

2.13 Receive and Transmit Latency

The transmit FIFO contains twenty-four 64-byte cells and the receive FIFO contains sixty-eight 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH cells (configurable through the FIFO control register, FIFOCONTROL) or a complete packet are available in the FIFO.

Transmit underrun cannot occur for packet sizes of TXCELLTHRESH × 64 bytes (or less). For larger packet sizes, transmit underrun can occur if the memory latency is greater than the time required to transmit a 64-byte cell on the wire; this is 0.512 ms in 1 Gbit mode, 5.12 ms in 100 Mbps mode, and

51.2ms in 10 Mbps mode. The memory latency time includes all buffer descriptor reads for the entire cell data. The EMAC transmit FIFO uses 24 cells; thus, underrun cannot happen for a normal size packet (less than 1536 packet bytes). Cell transmission can be configured to start only after an entire packet is contained in the FIFO; for a maximum-size packet, set the TXCELLTHRESH field to the maximum possible value of 24.

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 49

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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramClock Control Industry Standards Compliance StatementMII Clocking Memory Map Signal DescriptionsMedia Independent Interface MII Connections Signal Type Description Emac and Mdio Signals for MII InterfacePin Multiplexing Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors WordField Field Description Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber FlagInternal Memory Emac Control ModuleBus Arbiter CPUTransmit Pulse Interrupt Interrupt ControlReceive Pulse Interrupt Miscellaneous Pulse Interrupt Receive Threshold Pulse InterruptInterrupt Pacing Mdio Module Components Mdio ModuleMdio Clock Generator Global PHY Detection and Link State MonitoringActive PHY Monitoring PHY Register User AccessMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeEmac Module Components Emac ModuleReceive DMA Engine Receive FifoMAC Receiver Clock and Reset LogicReceive Address Transmit DMA EngineEmac Module Operational Overview Data Reception Media Independent Interface MIIReceive Control Receive Inter-Frame IntervalIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Hardware Receive QOS Support Receive Address MatchingReceive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeReceive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module InitializationEmac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportReceive Threshold Interrupts Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Statistics Interrupt Host Error InterruptMdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt ProcessingEmulation Considerations Power ManagementEmulation Control Soft Free DescriptionSlave Vbus Emac Control Module RegistersAcronym Register Description Bit Field Value DescriptionSoftreset Emac Control Module Software Reset Register CmsoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft FreeIntpaceen Emac Control Module Interrupt Control Register CmintctrlIntprescale Rxpulseen RxthreshenTxpulseen Bit Field Statpendinten Hostpendinten Linkinten UserintenStatpendinten Rxpulseinttstat Rxthreshinttstat31-8 Reserved TXPULSEINTTSTATn TxpulseinttstatStatpendintstat Statpendintstat Hostpendintstat Linkintstat UserintstatTximax RximaxManagement Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon LinkselMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxident Receive Identification and Version Register RxidverRxmajorver Rxminorver RxmajorverReceive Teardown Register Rxteardown Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field DescriptionsTX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions StatpendRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask HostmaskRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolRxbufferflowen TxflowenLoopback FullduplexMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusRxqosact Fifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsSoft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Matchfilt Channel MACADDR0 MACADDR1 ValidMAC Index Register Macindex MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register TxbcastframesDeferred Transmit Frames Register Txdeferred Pause Transmit Frames Register TxpauseframesTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register TxsinglecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Underrun Error Register TxunderrunTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register NetoctetsAppendix a Glossary Term Definition Physical Layer DefinitionsReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid
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