Texas Instruments TMS320DM36X manual Receive Overrun, Middle of Frame Overrun Treatment

Page 48

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Table 4. Receive Frame Treatment Summary (continued)

Address Match

RXCAFEN

RXCEFEN

RXCMFEN

RXCSFEN

Receive Frame Treatment

1

X

1

1

0

Proper/oversize/jabber/code/align/CRC data and

 

 

 

 

 

control frames transferred to address match

 

 

 

 

 

channel. No undersized/fragment frames are

 

 

 

 

 

transferred.

 

 

 

 

 

 

1

X

1

1

1

All address matching frames with and without

 

 

 

 

 

errors transferred to the address match channel

 

 

 

 

 

 

2.11.9Receive Overrun

The types of receive overrun are:

•FIFO start of frame overrun (FIFO_SOF)

•FIFO middle of frame overrun (FIFO_MOF)

•DMA start of frame overrun (DMA_SOF)

•DMA middle of frame overrun (DMA_MOF)

The statistics counters used to track these types of receive overrun are:

•Receive start of frame overruns register (RXSOFOVERRUNS)

•Receive middle of frame overruns register (RXMOFOVERRUNS)

•Receive DMA overruns register (RXDMAOVERRUNS)

Start of frame overruns happen when there are no resources available when frame reception begins. Start of frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.

Middle of frame overruns happen when there are some resources to start the frame reception, but the resources run out during frame reception. In normal operation, a frame that overruns after starting the frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) affects overrun frame treatment. Table 5 shows how the overrun condition is handled for the middle of frame overrun.

Table 5. Middle of Frame Overrun Treatment

Address Match

RXCAFEN

RXCEFEN

Middle of Frame Overrun Treatment

0

0

X

Overrun frame filtered.

 

 

 

 

0

1

0

Overrun frame filtered.

 

 

 

 

0

1

1

As much frame data as possible is transferred to the promiscuous channel

 

 

 

until overrun. The appropriate overrun statistic(s) is incremented and the

 

 

 

OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note

 

 

 

that the RXMAXLEN number of bytes cannot be reached for an overrun to

 

 

 

occur (it would be truncated and be a jabber or oversize).

 

 

 

 

1

X

0

Overrun frame filtered with the appropriate overrun statistic(s) incremented.

 

 

 

 

1

X

1

As much frame data as possible is transferred to the address match

 

 

 

channel until overrun. The appropriate overrun statistic(s) is incremented

 

 

 

and the OVERRUN flag is set in the SOP buffer descriptor. Note that the

 

 

 

RXMAXLEN number of bytes cannot be reached for an overrun to occur (it

 

 

 

would be truncated).

 

 

 

 

48 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B –March 2009 –Revised December 2010

(MDIO)

Submit Documentation Feedback

 

© 2009–2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramIndustry Standards Compliance Statement Clock ControlMII Clocking Signal Descriptions Memory MapMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface Signal Type DescriptionPin Multiplexing Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors WordBasic Descriptor Description Field Field DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module Internal MemoryBus Arbiter CPUInterrupt Control Transmit Pulse InterruptReceive Pulse Interrupt Receive Threshold Pulse Interrupt Miscellaneous Pulse InterruptInterrupt Pacing Mdio Module Mdio Module ComponentsMdio Clock Generator Global PHY Detection and Link State MonitoringPHY Register User Access Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic MAC ReceiverReceive Address Transmit DMA EngineEmac Module Operational Overview Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS SupportHost Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization CodeEmac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsReceive Threshold Interrupts Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Host Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Soft Free DescriptionEmac Control Module Registers Slave VbusAcronym Register Description Bit Field Value DescriptionEmac Control Module Software Reset Register Cmsoftreset SoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft FreeEmac Control Module Interrupt Control Register Cmintctrl IntpaceenIntprescale Rxthreshen RxpulseenTxpulseen Statpendinten Hostpendinten Linkinten Userinten Bit FieldStatpendinten Rxthreshinttstat RxpulseinttstatTxpulseinttstat 31-8 Reserved TXPULSEINTTSTATnStatpendintstat Hostpendintstat Linkintstat Userintstat StatpendintstatRximax TximaxMdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver RxidentRxmajorver Rxminorver RxmajorverReceive Control Register Rxcontrol Receive Teardown Register RxteardownReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field DescriptionsTransmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC End Of Interrupt Vector Register MaceoivectorMAC Input Vector Register Macinvector Field Descriptions StatpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsTxflowen RxbufferflowenLoopback FullduplexMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsRxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 ValidMAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register TxsinglecollTransmit Underrun Error Register Txunderrun Transmit Carrier Sense Errors Register TxcarriersenseTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register RxdmaoverrunsAppendix a Glossary Physical Layer Definitions Term DefinitionDocument Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid
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