Texas Instruments TMS320DM36X manual Offset Acronym Register Description

Page 84

Ethernet Media Access Controller (EMAC) Registerswww.ti.com

Table 37. Ethernet Media Access Controller (EMAC) Registers (continued)

Offset

Acronym

Register Description

Section

164h

MACSTATUS

MAC Status Register

Section 5.30

168h

EMCONTROL

Emulation Control Register

Section 5.31

16Ch

FIFOCONTROL

FIFO Control Register

Section 5.32

170h

MACCONFIG

MAC Configuration Register

Section 5.33

174h

SOFTRESET

Soft Reset Register

Section 5.34

1D0h

MACSRCADDRLO

MAC Source Address Low Bytes Register

Section 5.35

1D4h

MACSRCADDRHI

MAC Source Address High Bytes Register

Section 5.36

1D8h

MACHASH1

MAC Hash Address Register 1

Section 5.37

1DCh

MACHASH2

MAC Hash Address Register 2

Section 5.38

1E0h

BOFFTEST

Back Off Test Register

Section 5.39

1E4h

TPACETEST

Transmit Pacing Algorithm Test Register

Section 5.40

1E8h

RXPAUSE

Receive Pause Timer Register

Section 5.41

1ECh

TXPAUSE

Transmit Pause Timer Register

Section 5.42

500h

MACADDRLO

MAC Address Low Bytes Register, Used in Receive Address Matching

Section 5.43

504h

MACADDRHI

MAC Address High Bytes Register, Used in Receive Address Matching

Section 5.44

508h

MACINDEX

MAC Index Register

Section 5.45

600h

TX0HDP

Transmit Channel 0 DMA Head Descriptor Pointer Register

Section 5.46

604h

TX1HDP

Transmit Channel 1 DMA Head Descriptor Pointer Register

Section 5.46

608h

TX2HDP

Transmit Channel 2 DMA Head Descriptor Pointer Register

Section 5.46

60Ch

TX3HDP

Transmit Channel 3 DMA Head Descriptor Pointer Register

Section 5.46

610h

TX4HDP

Transmit Channel 4 DMA Head Descriptor Pointer Register

Section 5.46

614h

TX5HDP

Transmit Channel 5 DMA Head Descriptor Pointer Register

Section 5.46

618h

TX6HDP

Transmit Channel 6 DMA Head Descriptor Pointer Register

Section 5.46

61Ch

TX7HDP

Transmit Channel 7 DMA Head Descriptor Pointer Register

Section 5.46

620h

RX0HDP

Receive Channel 0 DMA Head Descriptor Pointer Register

Section 5.47

624h

RX1HDP

Receive Channel 1 DMA Head Descriptor Pointer Register

Section 5.47

628h

RX2HDP

Receive Channel 2 DMA Head Descriptor Pointer Register

Section 5.47

62Ch

RX3HDP

Receive Channel 3 DMA Head Descriptor Pointer Register

Section 5.47

630h

RX4HDP

Receive Channel 4 DMA Head Descriptor Pointer Register

Section 5.47

634h

RX5HDP

Receive Channel 5 DMA Head Descriptor Pointer Register

Section 5.47

638h

RX6HDP

Receive Channel 6 DMA Head Descriptor Pointer Register

Section 5.47

63Ch

RX7HDP

Receive Channel 7 DMA Head Descriptor Pointer Register

Section 5.47

640h

TX0CP

Transmit Channel 0 Completion Pointer Register

Section 5.48

644h

TX1CP

Transmit Channel 1 Completion Pointer Register

Section 5.48

648h

TX2CP

Transmit Channel 2 Completion Pointer Register

Section 5.48

64Ch

TX3CP

Transmit Channel 3 Completion Pointer Register

Section 5.48

650h

TX4CP

Transmit Channel 4 Completion Pointer Register

Section 5.48

654h

TX5CP

Transmit Channel 5 Completion Pointer Register

Section 5.48

658h

TX6CP

Transmit Channel 6 Completion Pointer Register

Section 5.48

65Ch

TX7CP

Transmit Channel 7 Completion Pointer Register

Section 5.48

660h

RX0CP

Receive Channel 0 Completion Pointer Register

Section 5.49

664h

RX1CP

Receive Channel 1 Completion Pointer Register

Section 5.49

668h

RX2CP

Receive Channel 2 Completion Pointer Register

Section 5.49

66Ch

RX3CP

Receive Channel 3 Completion Pointer Register

Section 5.49

670h

RX4CP

Receive Channel 4 Completion Pointer Register

Section 5.49

674h

RX5CP

Receive Channel 5 Completion Pointer Register

Section 5.49

678h

RX6CP

Receive Channel 6 Completion Pointer Register

Section 5.49

 

 

 

 

84 Ethernet Media Access Controller (EMAC)/Management Data Input/Output

SPRUFI5B –March 2009 –Revised December 2010

(MDIO)

Submit Documentation Feedback

 

© 2009–2010, Texas Instruments Incorporated

Page 83 Page 85
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Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramIndustry Standards Compliance Statement Clock ControlMII Clocking Signal Descriptions Memory MapMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface Signal Type DescriptionPin Multiplexing Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors WordBasic Descriptor Description Field Field DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module Internal MemoryBus Arbiter CPUInterrupt Control Transmit Pulse InterruptReceive Pulse Interrupt Receive Threshold Pulse Interrupt Miscellaneous Pulse InterruptInterrupt Pacing Mdio Module Mdio Module ComponentsMdio Clock Generator Global PHY Detection and Link State MonitoringPHY Register User Access Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic MAC ReceiverReceive Address Transmit DMA EngineEmac Module Operational Overview Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS SupportHost Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization CodeEmac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsReceive Threshold Interrupts Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Host Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Soft Free DescriptionEmac Control Module Registers Slave VbusAcronym Register Description Bit Field Value DescriptionEmac Control Module Software Reset Register Cmsoftreset SoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft FreeEmac Control Module Interrupt Control Register Cmintctrl IntpaceenIntprescale Rxthreshen RxpulseenTxpulseen Statpendinten Hostpendinten Linkinten Userinten Bit FieldStatpendinten Rxthreshinttstat RxpulseinttstatTxpulseinttstat 31-8 Reserved TXPULSEINTTSTATnStatpendintstat Hostpendintstat Linkintstat Userintstat StatpendintstatRximax TximaxMdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver RxidentRxmajorver Rxminorver RxmajorverReceive Control Register Rxcontrol Receive Teardown Register RxteardownReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field DescriptionsTransmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC End Of Interrupt Vector Register MaceoivectorMAC Input Vector Register Macinvector Field Descriptions StatpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsTxflowen RxbufferflowenLoopback FullduplexMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsRxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 ValidMAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register TxsinglecollTransmit Underrun Error Register Txunderrun Transmit Carrier Sense Errors Register TxcarriersenseTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register RxdmaoverrunsAppendix a Glossary Physical Layer Definitions Term DefinitionDocument Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid
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