Texas Instruments TMS320DM36X manual Network Statistics Registers

Page 85

www.ti.comEthernet Media Access Controller (EMAC) Registers

Table 37. Ethernet Media Access Controller (EMAC) Registers (continued)

Offset

Acronym

Register Description

Section

67Ch

RX7CP

Receive Channel 7 Completion Pointer Register

Section 5.49

 

 

 

 

 

 

Network Statistics Registers

 

200h

RXGOODFRAMES

Good Receive Frames Register

Section 5.50.1

204h

RXBCASTFRAMES

Broadcast Receive Frames Register

Section 5.50.2

208h

RXMCASTFRAMES

Multicast Receive Frames Register

Section 5.50.3

20Ch

RXPAUSEFRAMES

Pause Receive Frames Register

Section 5.50.4

210h

RXCRCERRORS

Receive CRC Errors Register

Section 5.50.5

214h

RXALIGNCODEERRORS

Receive Alignment/Code Errors Register

Section 5.50.6

218h

RXOVERSIZED

Receive Oversized Frames Register

Section 5.50.7

21Ch

RXJABBER

Receive Jabber Frames Register

Section 5.50.8

220h

RXUNDERSIZED

Receive Undersized Frames Register

Section 5.50.9

224h

RXFRAGMENTS

Receive Frame Fragments Register

Section 5.50.10

228h

RXFILTERED

Filtered Receive Frames Register

Section 5.50.11

22Ch

RXQOSFILTERED

Receive QOS Filtered Frames Register

Section 5.50.12

230h

RXOCTETS

Receive Octet Frames Register

Section 5.50.13

234h

TXGOODFRAMES

Good Transmit Frames Register

Section 5.50.14

238h

TXBCASTFRAMES

Broadcast Transmit Frames Register

Section 5.50.15

23Ch

TXMCASTFRAMES

Multicast Transmit Frames Register

Section 5.50.16

240h

TXPAUSEFRAMES

Pause Transmit Frames Register

Section 5.50.17

244h

TXDEFERRED

Deferred Transmit Frames Register

Section 5.50.18

248h

TXCOLLISION

Transmit Collision Frames Register

Section 5.50.19

24Ch

TXSINGLECOLL

Transmit Single Collision Frames Register

Section 5.50.20

250h

TXMULTICOLL

Transmit Multiple Collision Frames Register

Section 5.50.21

254h

TXEXCESSIVECOLL

Transmit Excessive Collision Frames Register

Section 5.50.22

258h

TXLATECOLL

Transmit Late Collision Frames Register

Section 5.50.23

25Ch

TXUNDERRUN

Transmit Underrun Error Register

Section 5.50.24

260h

TXCARRIERSENSE

Transmit Carrier Sense Errors Register

Section 5.50.25

264h

TXOCTETS

Transmit Octet Frames Register

Section 5.50.26

268h

FRAME64

Transmit and Receive 64 Octet Frames Register

Section 5.50.27

26Ch

FRAME65T127

Transmit and Receive 65 to 127 Octet Frames Register

Section 5.50.28

270h

FRAME128T255

Transmit and Receive 128 to 255 Octet Frames Register

Section 5.50.29

274h

FRAME256T511

Transmit and Receive 256 to 511 Octet Frames Register

Section 5.50.30

278h

FRAME512T1023

Transmit and Receive 512 to 1023 Octet Frames Register

Section 5.50.31

27Ch

FRAME1024TUP

Transmit and Receive 1024 to RXMAXLEN Octet Frames Register

Section 5.50.32

280h

NETOCTETS

Network Octet Frames Register

Section 5.50.33

284h

RXSOFOVERRUNS

Receive FIFO or DMA Start of Frame Overruns Register

Section 5.50.34

288h

RXMOFOVERRUNS

Receive FIFO or DMA Middle of Frame Overruns Register

Section 5.50.35

28Ch

RXDMAOVERRUNS

Receive DMA Overruns Register

Section 5.50.36

 

 

 

 

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 85

Submit Documentation Feedback

(MDIO)

 

© 2009–2010, Texas Instruments Incorporated

Page 84 Page 86
Image 85
Page 84 Page 86
Contents Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramClock Control Industry Standards Compliance StatementMII Clocking Memory Map Signal DescriptionsMedia Independent Interface MII Connections Signal Type Description Emac and Mdio Signals for MII InterfacePin Multiplexing Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors WordField Field Description Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format Buffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber FlagInternal Memory Emac Control ModuleBus Arbiter CPUTransmit Pulse Interrupt Interrupt ControlReceive Pulse Interrupt Miscellaneous Pulse Interrupt Receive Threshold Pulse InterruptInterrupt Pacing Mdio Module Components Mdio ModuleMdio Clock Generator Global PHY Detection and Link State MonitoringActive PHY Monitoring PHY Register User AccessMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeEmac Module Components Emac ModuleReceive DMA Engine Receive FifoMAC Receiver Clock and Reset LogicReceive Address Transmit DMA EngineEmac Module Operational Overview Data Reception Media Independent Interface MIIReceive Control Receive Inter-Frame IntervalIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Hardware Receive QOS Support Receive Address MatchingReceive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeReceive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module InitializationEmac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportReceive Threshold Interrupts Transmit Packet Completion InterruptsReceive Packet Completion Interrupts Statistics Interrupt Host Error InterruptMdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt ProcessingEmulation Considerations Power ManagementEmulation Control Soft Free DescriptionSlave Vbus Emac Control Module RegistersAcronym Register Description Bit Field Value DescriptionSoftreset Emac Control Module Software Reset Register CmsoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft FreeIntpaceen Emac Control Module Interrupt Control Register CmintctrlIntprescale Rxpulseen RxthreshenTxpulseen Bit Field Statpendinten Hostpendinten Linkinten UserintenStatpendinten Rxpulseinttstat Rxthreshinttstat31-8 Reserved TXPULSEINTTSTATn TxpulseinttstatStatpendintstat Statpendintstat Hostpendintstat Linkintstat UserintstatTximax RximaxManagement Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon LinkselMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxident Receive Identification and Version Register RxidverRxmajorver Rxminorver RxmajorverReceive Teardown Register Rxteardown Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field DescriptionsTX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions StatpendRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask HostmaskRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolRxbufferflowen TxflowenLoopback FullduplexMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusRxqosact Fifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsSoft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Matchfilt Channel MACADDR0 MACADDR1 ValidMAC Index Register Macindex MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5TXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register TxbcastframesDeferred Transmit Frames Register Txdeferred Pause Transmit Frames Register TxpauseframesTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register TxsinglecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Underrun Error Register TxunderrunTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register TxoctetsSubmit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register NetoctetsAppendix a Glossary Term Definition Physical Layer DefinitionsReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid
Related manuals
Manual 18 pages 38.41 Kb
Top Page Image Contents