Sigma DE2-70 manual Using the Expansion Header

Page 44

DE2-70 User Manual

LCD_DATA[5]	PIN_C2	LCD Data[5]

LCD_DATA[6]	PIN_C3	LCD Data[6]

LCD_DATA[7]	PIN_B2	LCD Data[7]

LCD_RW	PIN_F3	LCD Read/Write Select, 0 = Write, 1 = Read

LCD_EN	PIN_E2	LCD Enable

LCD_RS	PIN_F2	LCD Command/Data Select, 0 = Command, 1 = Data

LCD_ON	PIN_F1	LCD Power ON/OFF

LCD_BLON	PIN_G3	LCD Back Light ON/OFF

Table 5.6. Pin assignments for the LCD module.

Note that the current LCD modules used on DE2/DE2-70 boards do not have backlight. Therefore the LCD_BLON signal should not be used in users’ design projects.

5.6 Using the Expansion Header

The DE2-70 Board provides two 40-pin expansion headers. Each header connects directly to 36 pins of the Cyclone II FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins. Among these 36 I/O pins, 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA.

The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, or 1.8V using JP1. Because the expansion I/Os are connected to the BANK 5 of the FPGA and the VCCIO voltage (VCCIO5) of this bank is controlled by the header JP1, users can use a jumper to select the input voltage of VCCIO5 to 3.3V, 2.5V, and 1.8V to control the voltage level of the I/O pins. Table 5.7 lists the jumper settings of the JP1. The pin-outs of the JP1 appear in the Figure 5.10.

Finally, Figure 5.11 shows the related schematics. Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages. The figure shows the protection circuitry for only two of the pins on each header, but this circuitry is included for all 72 data pins. Table 5.8 gives the pin assignments.

	JP1 Jumper Settings	Supplied Voltage to VCCIO5	IO Voltage of Expansion
	JP1 Jumper Settings	Supplied Voltage to VCCIO5	Headers (J4/J5)
			Headers (J4/J5)

	Short Pins 1 and 2	1.8V	1.8V

	Short Pins 3 and 4	2.5V	2.5V

	Short Pins 5 and 6	3.3V	3.3V

Table 5.7. Voltage level setting of the expansion headers using JP1.

41

Image 44

Contents Copyright 2007 Terasic Technologies Contents Appendix Package Contents DE2-70 PackageDE2-70 Board Assembly Feet for the DE2-70 boardGetting Help Altera DE2-70 Board Layout and ComponentsBlock Diagram of the DE2-70 Board Cyclone II 2C70 Fpga Ssram Audio Codec Power-up the DE2-70 Board Serial portsLCD display shows Welcome to the Altera DE2-70 Control Panel Setup DE2-70 Control PanelPage Controlling the LEDs, 7-Segment Displays and LCD Display Controlling 7-SEG display Switches and Buttons SDRAM/SSRAM/Flash Controller and Programmer Page Press Load Memory Content to a File button USB MonitoringPS2 Device USB Mouse Monitoring ToolSD Card 10. Reading the SD card Identification and Specification Audio Playing and RecordingPage Overall Structure of the DE2-70 Control Panel 13. The block diagram of the DE2-70 control panel Video Utility Setup DE2-70 Video UtilityVGA Display DE2-70 Video Utility windowVideo Capture Displaying selected image file on VGA MonitorOverall Structure of the DE2-70 Video Utility Video Capturing ToolVideo Capture Block Diagram Using the DE2-70 Board Configuring the Cyclone II FpgaFpga Using the LEDs and Switches Switch debouncingSchematic diagram of the pushbutton and toggle switches Schematic diagram of the LEDs Pin assignments for the toggle switches Using the 7-segment Displays Schematic diagram of the 7-segment displaysPINAD10 Clock Circuitry Block diagram of the clock distribution Using the LCD Module LcdonUsing the Expansion Header JP1 PIND29 Pin assignments for the expansion headers Using VGA Rset13. VGA horizontal timing specification 11. ADV7123 pin assignments Using the 24-bit Audio Codec I2C Address Read is 0x34 I2C Address Write isRS-232 Serial Port 10 PS/2 Serial PortPS/2 schematic Fast Ethernet Network Controller17. Fast Ethernet schematic TV Decoder 18. TV Decoder schematic Implementing a TV Encoder Bit VGA DACUsing USB Host and Device OTGD15 OTGD14 OTGD13 OTGD12 OTGD11 OTGD10Using IrDA Using SDRAM/SRAM/Flash IrDA schematic22. Sdram schematic 23. Ssram schematic PINAA4 DRAM0CKE PINAA8 19. Sdram pin assignments SRAMDQ8 PINAK17 20. Ssram pin assignments 21. Flash pin assignments DE2-70 Factory Configuration Examples of Advanced DemonstrationsTV Box Demonstration Block diagram of the TV box demonstration Setup for the TV box demonstration TV Box Picture in Picture PIP DemonstrationBit stream used DE270TVPIP.sof or DE270TVPIP.pof Setup for the TV box PIP demonstration USB Paintbrush Block diagram of the USB paintbrush demonstration Setup for the USB paintbrush demonstration USB DeviceBlock diagram of the USB device demonstration Setup for the USB device demonstration Karaoke MachineBit stream used DE2-70i2sound.sof or DE2-70i2sound.pof 10. The setup for the Karaoke Machine Ethernet Packet Sending/Receiving11. Packet sending and receiving using the Nios II processor 12. The setup for the Ethernet demonstration SD Card Music Player13. Block diagram of the SD music player demonstration Demonstration Setup, File Locations, and Instructions 16 illustrates the setup for this demonstration Music Synthesizer Demonstration17 illustrates the setup for this demonstration Usage of the switches, pushbuttons KEYs PS/2 Keyboard 16. The Setup of the Music Synthesizer Demonstration Audio Recording and Playing Nios II IDESopc Toggle switch setting for audio recorder and player Revision History Copyright Statement