Sigma DE2-70 manual Using the 24-bit Audio Codec, I2C Address Read is 0x34 I2C Address Write is

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DE2-70 User Manual

5.8 Using the 24-bit Audio CODEC

The DE2-70 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC (enCOder/DECoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate adjustable from 8 kHz to 96 kHz. The WM8731 is controlled by a serial I2C bus interface, which is connected to pins on the Cyclone II FPGA. A schematic diagram of the audio circuitry is shown in Figure 5.14, and the FPGA pin assignments are listed in Table 5.12. Detailed information for using the WM8731 codec is available in its datasheet, which can be found on the manufacturer's web site, or in the Datasheet/Audio CODEC folder on the DE2-70 System CD-ROM.

	C38	1u			R99	4.7K
		C39	1u		R100	4.7K
VCC33 VCC33
				R101	R102
R108	R109			4.7K	4.7K
R108	R109
2K	2K			AGND AGND
I2C_SDAT				AGND AGND
I2C_SDAT
I2C_SCLK			R103	330

J11			LINE IN
LCN R RCN L DNG



5	2	4	1	3		PHONE JACK B

				AGND
J10			MIC IN
LC		RC		DN
LC		RC		DN

I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35

A_VCC33

AGND

AUD_XCK

AUD_BCLK

AUD_DACDAT

AUD_DACLRCK

AUD_ADCDAT

AUD_ADCLRCK

	U13			28 27			26 25 24 23 22
	U13
				LKC IND BS ED INE INE INIC S S C O LLIN LIN M M R
1	XTI/MCLK
2	XTI/MCLK
2	XTO
3	XTO
3	DCVDD						WM8731
4	DCVDD
4	DGND
5	DGND
5	DBVDD
6	DBVDD
6	CLKOUT
7	CLKOUT
7	BCLK
		DES TA KCLR TA KCLR D TU TU OPX DCA CA DCD CD DVP OPLH OPH E D D A A H R
				8		9
	29						10	11	12	13	14
	29						10	11	12	13	14
AGND
AGND								A_VCC33
								A_VCC33

MBIAS VMID AGND AVDD ROUT LOUT HPGND

					C40
					1u
21	C41	10u	R104	680
20	C41	10u		C42	R105
19			AGND	C42	R105
18	A_VCC33		AGND
18				1n	47K
17
17
16
15	AGND			AGND AGND
	AGND

	C43	100u
		C44	100u
				R106	R107
				47K	47K

	N R N L G

	5	2	4	1	3		PHONE JACK P

					AGND
	J12 LINE OUT
	LCN R RCN L DNG

							PHONE JACK G

	5	2	4	1	3
	5	2	4	1	3



					AGND

		AGND AGND
	Figure 5.14. Audio CODEC schematic.

Signal Name	FPGA Pin No.	Description

AUD_ADCLRCK	PIN_F19	Audio CODEC ADC LR Clock

AUD_ADCDAT	PIN_E19	Audio CODEC ADC Data

AUD_DACLRCK	PIN_G18	Audio CODEC DAC LR Clock

AUD_DACDAT	PIN_F18	Audio CODEC DAC Data

AUD_XCK	PIN_D17	Audio CODEC Chip Clock

AUD_BCLK	PIN_E17	Audio CODEC Bit-Stream Clock

I2C_SCLK	PIN_J18	I2C Data

I2C_SDAT	PIN_H18	I2C Clock

Table 5.12. Audio CODEC pin assignments.

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Contents Copyright 2007 Terasic Technologies Contents Appendix DE2-70 Package Package ContentsFeet for the DE2-70 board DE2-70 Board AssemblyGetting Help Layout and Components Altera DE2-70 BoardBlock Diagram of the DE2-70 Board Cyclone II 2C70 Fpga Ssram Audio Codec Serial ports Power-up the DE2-70 BoardLCD display shows Welcome to the Altera DE2-70 DE2-70 Control Panel Control Panel SetupPage Controlling the LEDs, 7-Segment Displays and LCD Display Controlling 7-SEG display Switches and Buttons SDRAM/SSRAM/Flash Controller and Programmer Page USB Monitoring Press Load Memory Content to a File buttonUSB Mouse Monitoring Tool PS2 DeviceSD Card Audio Playing and Recording 10. Reading the SD card Identification and SpecificationPage Overall Structure of the DE2-70 Control Panel 13. The block diagram of the DE2-70 control panel DE2-70 Video Utility Video Utility SetupDE2-70 Video Utility window VGA DisplayDisplaying selected image file on VGA Monitor Video CaptureVideo Capturing Tool Overall Structure of the DE2-70 Video UtilityVideo Capture Block Diagram Configuring the Cyclone II Fpga Using the DE2-70 BoardFpga Switch debouncing Using the LEDs and SwitchesSchematic diagram of the pushbutton and toggle switches Schematic diagram of the LEDs Pin assignments for the toggle switches Schematic diagram of the 7-segment displays Using the 7-segment DisplaysPINAD10 Clock Circuitry Block diagram of the clock distribution Lcdon Using the LCD ModuleUsing the Expansion Header JP1 PIND29 Pin assignments for the expansion headers Rset Using VGA13. VGA horizontal timing specification 11. ADV7123 pin assignments I2C Address Read is 0x34 I2C Address Write is Using the 24-bit Audio Codec10 PS/2 Serial Port RS-232 Serial PortFast Ethernet Network Controller PS/2 schematic17. Fast Ethernet schematic TV Decoder 18. TV Decoder schematic Bit VGA DAC Implementing a TV EncoderOTGD15 OTGD14 OTGD13 OTGD12 OTGD11 OTGD10 Using USB Host and DeviceUsing IrDA IrDA schematic Using SDRAM/SRAM/Flash22. Sdram schematic 23. Ssram schematic PINAA4 DRAM0CKE PINAA8 19. Sdram pin assignments SRAMDQ8 PINAK17 20. Ssram pin assignments 21. Flash pin assignments Examples of Advanced Demonstrations DE2-70 Factory ConfigurationTV Box Demonstration Block diagram of the TV box demonstration TV Box Picture in Picture PIP Demonstration Setup for the TV box demonstrationBit stream used DE270TVPIP.sof or DE270TVPIP.pof Setup for the TV box PIP demonstration USB Paintbrush Block diagram of the USB paintbrush demonstration USB Device Setup for the USB paintbrush demonstrationBlock diagram of the USB device demonstration Karaoke Machine Setup for the USB device demonstrationBit stream used DE2-70i2sound.sof or DE2-70i2sound.pof Ethernet Packet Sending/Receiving 10. The setup for the Karaoke Machine11. Packet sending and receiving using the Nios II processor SD Card Music Player 12. The setup for the Ethernet demonstration13. Block diagram of the SD music player demonstration Demonstration Setup, File Locations, and Instructions Music Synthesizer Demonstration 16 illustrates the setup for this demonstration17 illustrates the setup for this demonstration Usage of the switches, pushbuttons KEYs PS/2 Keyboard 16. The Setup of the Music Synthesizer Demonstration Nios II IDE Audio Recording and PlayingSopc Toggle switch setting for audio recorder and player Copyright Statement Revision History