Sigma DE2-70 manual VGA horizontal timing specification

Page 49

DE2-70 User Manual

found on the manufacturer's web site, or in the Datasheet/VGA DAC folder on the DE2-70 System CD-ROM. The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table

5.11.An example of code that drives a VGA display is described in Sections 6.2, 6.3 and 6.4.

Figure 5.13. VGA horizontal timing specification.

VGA mode

 

Horizontal Timing Spec

 

 

 

 

 

 

 

 

 

Configuration

Resolution(HxV)

a(us)

b(us)

c(us)

d(us)

Pixel clock(Mhz)

 

 

 

 

 

 

 

 

VGA(60Hz)

640x480

3.8

1.9

25.4

0.6

25

(640/c)

 

 

 

 

 

 

 

 

VGA(85Hz)

640x480

1.6

2.2

17.8

1.6

36

(640/c)

 

 

 

 

 

 

 

 

SVGA(60Hz)

800x600

3.2

2.2

20

1

40

(800/c)

 

 

 

 

 

 

 

 

SVGA(75Hz)

800x600

1.6

3.2

16.2

0.3

49

(800/c)

 

 

 

 

 

 

 

 

SVGA(85Hz)

800x600

1.1

2.7

14.2

0.6

56

(800/c)

 

 

 

 

 

 

 

 

XGA(60Hz)

1024x768

2.1

2.5

15.8

0.4

65

(1024/c)

 

 

 

 

 

 

 

 

XGA(70Hz)

1024x768

1.8

1.9

13.7

0.3

75

(1024/c)

 

 

 

 

 

 

 

 

XGA(85Hz)

1024x768

1.0

2.2

10.8

0.5

95

(1024/c)

 

 

 

 

 

 

 

 

1280x1024(60Hz)

1280x1024

1.0

2.3

11.9

0.4

108

(1280/c)

 

 

 

 

 

 

 

 

Table 5.9. VGA horizontal timing specification.

 

VGA mode

 

Vertical Timing Spec

 

 

 

 

 

 

 

Configuration

Resolution (HxV)

a(lines)

b(lines)

c(lines)

d(lines)

 

 

 

 

 

 

VGA(60Hz)

640x480

2

33

480

10

 

 

 

 

 

 

VGA(85Hz)

640x480

3

25

480

1

 

 

 

 

 

 

SVGA(60Hz)

800x600

4

23

600

1

 

 

 

 

 

 

SVGA(75Hz)

800x600

3

21

600

1

 

 

 

 

 

 

SVGA(85Hz)

800x600

3

27

600

1

 

 

 

 

 

 

XGA(60Hz)

1024x768

6

29

768

3

 

 

 

 

 

 

XGA(70Hz)

1024x768

6

29

768

3

 

 

 

 

 

 

XGA(85Hz)

1024x768

3

36

768

1

 

 

 

 

 

 

1280x1024(60Hz)

1280x1024

3

38

1024

1

 

 

 

 

 

 

Table 5.10. VGA vertical timing specification.

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Contents Copyright 2007 Terasic Technologies Contents Appendix DE2-70 Package Package ContentsFeet for the DE2-70 board DE2-70 Board AssemblyGetting Help Layout and Components Altera DE2-70 BoardBlock Diagram of the DE2-70 Board Cyclone II 2C70 Fpga Ssram Audio Codec Serial ports Power-up the DE2-70 BoardLCD display shows Welcome to the Altera DE2-70 DE2-70 Control Panel Control Panel SetupPage Controlling the LEDs, 7-Segment Displays and LCD Display Controlling 7-SEG display Switches and Buttons SDRAM/SSRAM/Flash Controller and Programmer Page USB Monitoring Press Load Memory Content to a File buttonUSB Mouse Monitoring Tool PS2 DeviceSD Card Audio Playing and Recording 10. Reading the SD card Identification and SpecificationPage Overall Structure of the DE2-70 Control Panel 13. The block diagram of the DE2-70 control panel DE2-70 Video Utility Video Utility SetupDE2-70 Video Utility window VGA DisplayDisplaying selected image file on VGA Monitor Video CaptureVideo Capturing Tool Overall Structure of the DE2-70 Video UtilityVideo Capture Block Diagram Configuring the Cyclone II Fpga Using the DE2-70 BoardFpga Switch debouncing Using the LEDs and SwitchesSchematic diagram of the pushbutton and toggle switches Schematic diagram of the LEDs Pin assignments for the toggle switches Schematic diagram of the 7-segment displays Using the 7-segment DisplaysPINAD10 Clock Circuitry Block diagram of the clock distribution Lcdon Using the LCD ModuleUsing the Expansion Header JP1 PIND29 Pin assignments for the expansion headers Rset Using VGA13. VGA horizontal timing specification 11. ADV7123 pin assignments I2C Address Read is 0x34 I2C Address Write is Using the 24-bit Audio Codec10 PS/2 Serial Port RS-232 Serial PortFast Ethernet Network Controller PS/2 schematic17. Fast Ethernet schematic TV Decoder 18. TV Decoder schematic Bit VGA DAC Implementing a TV EncoderOTGD15 OTGD14 OTGD13 OTGD12 OTGD11 OTGD10 Using USB Host and DeviceUsing IrDA IrDA schematic Using SDRAM/SRAM/Flash22. Sdram schematic 23. Ssram schematic PINAA4 DRAM0CKE PINAA8 19. Sdram pin assignments SRAMDQ8 PINAK17 20. Ssram pin assignments 21. Flash pin assignments Examples of Advanced Demonstrations DE2-70 Factory ConfigurationTV Box Demonstration Block diagram of the TV box demonstration TV Box Picture in Picture PIP Demonstration Setup for the TV box demonstrationBit stream used DE270TVPIP.sof or DE270TVPIP.pof Setup for the TV box PIP demonstration USB Paintbrush Block diagram of the USB paintbrush demonstration USB Device Setup for the USB paintbrush demonstrationBlock diagram of the USB device demonstration Karaoke Machine Setup for the USB device demonstrationBit stream used DE2-70i2sound.sof or DE2-70i2sound.pof Ethernet Packet Sending/Receiving 10. The setup for the Karaoke Machine11. Packet sending and receiving using the Nios II processor SD Card Music Player 12. The setup for the Ethernet demonstration13. Block diagram of the SD music player demonstration Demonstration Setup, File Locations, and Instructions Music Synthesizer Demonstration 16 illustrates the setup for this demonstration17 illustrates the setup for this demonstration Usage of the switches, pushbuttons KEYs PS/2 Keyboard 16. The Setup of the Music Synthesizer Demonstration Nios II IDE Audio Recording and PlayingSopc Toggle switch setting for audio recorder and player Copyright Statement Revision History
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