ENET_CS_N | PIN_C28 | DM9000A Chip Select |
|
|
|
ENET_INT | PIN_C27 | DM9000A Interrupt |
|
|
|
ENET_IOR_N | PIN_A28 | DM9000A Read |
|
|
|
ENET_IOW_N | PIN_B28 | DM9000A Write |
|
|
|
ENET_RESET_N | PIN_B29 | DM9000A Reset |
|
|
|
Table 5.15. Fast Ethernet pin assignments.
5.12 TV Decoder
The
The registers in both of the TV decoders can be programmed by a serial I2C bus, which is connected to the Cyclone II FPGA as indicated in Figure 5.18. Note that the I2C address of the TV decoder 1(U11) and TV decoder 2(U12) are 0x40 and 0x42 respectively. The pin assignments are listed in Table 5.16. Detailed information on the ADV7180 is available on the manufacturer’s web site, or in the Datasheet/TV Decoder folder on the
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