Sigma DE2-70 manual Clock Circuitry

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DE2-70 User Manual

HEX5_D[0]

PIN_M3

Seven Segment Digit 5[0]

 

 

 

HEX5_D[1]

PIN_L1

Seven Segment Digit 5[1]

 

 

 

HEX5_D[2]

PIN_L2

Seven Segment Digit 5[2]

 

 

 

HEX5_D[3]

PIN_L3

Seven Segment Digit 5[3]

 

 

 

HEX5_D[4]

PIN_K1

Seven Segment Digit 5[4]

 

 

 

HEX5_D[5]

PIN_K4

Seven Segment Digit 5[5]

 

 

 

HEX5_D[6]

PIN_K5

Seven Segment Digit 5[6]

 

 

 

HEX5_DP

PIN_K6

Seven Segment Decimal Point 5

 

 

 

HEX6_D[0]

PIN_H6

Seven Segment Digit 6[0]

 

 

 

HEX6_D[1]

PIN_H4

Seven Segment Digit 6[1]

 

 

 

HEX6_D[2]

PIN_H7

Seven Segment Digit 6[2]

 

 

 

HEX6_D[3]

PIN_H8

Seven Segment Digit 6[3]

 

 

 

HEX6_D[4]

PIN_G4

Seven Segment Digit 6[4]

 

 

 

HEX6_D[5]

PIN_F4

Seven Segment Digit 6[5]

 

 

 

HEX6_D[6]

PIN_E4

Seven Segment Digit 6[6]

 

 

 

HEX6_DP

PIN_K2

Seven Segment Decimal Point 6

 

 

 

HEX7_D[0]

PIN_K3

Seven Segment Digit 7[0]

 

 

 

HEX7_D[1]

PIN_J1

Seven Segment Digit 7[1]

 

 

 

HEX7_D[2]

PIN_J2

Seven Segment Digit 7[2]

 

 

 

HEX7_D[3]

PIN_H1

Seven Segment Digit 7[3]

 

 

 

HEX7_D[4]

PIN_H2

Seven Segment Digit 7[4]

 

 

 

HEX7_D[5]

PIN_H3

Seven Segment Digit 7[5]

 

 

 

HEX7_D[6]

PIN_G1

Seven Segment Digit 7[6]

 

 

 

HEX7_DP

PIN_G2

Seven Segment Decimal Point 7

 

 

 

Table 5.4. Pin assignments for the 7-segment displays.

5.4 Clock Circuitry

The DE2-70 board includes two oscillators that produce 28.86 MHz and 50 MHz clock signals. Both two clock signals are connected to the FPGA that are used for clocking the user logic. Also, the 28.86 MHz oscillator is used to drive the two TV decoders. The board also includes an SMA connector which can be used to connect an external clock source to the board. In addition, all these clock inputs are connected to the phase lock loops (PLL) clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit.

The clock distribution on the DE2-70 board is shown in Figure 5.8. The associated pin assignments for clock inputs to FPGA I/O pins are listed in Table 5.5.

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Contents Copyright 2007 Terasic Technologies Contents Appendix DE2-70 Package Package ContentsFeet for the DE2-70 board DE2-70 Board AssemblyGetting Help Layout and Components Altera DE2-70 BoardBlock Diagram of the DE2-70 Board Cyclone II 2C70 Fpga Ssram Audio Codec Serial ports Power-up the DE2-70 BoardLCD display shows Welcome to the Altera DE2-70 DE2-70 Control Panel Control Panel SetupPage Controlling the LEDs, 7-Segment Displays and LCD Display Controlling 7-SEG display Switches and Buttons SDRAM/SSRAM/Flash Controller and Programmer Page USB Monitoring Press Load Memory Content to a File buttonUSB Mouse Monitoring Tool PS2 DeviceSD Card Audio Playing and Recording 10. Reading the SD card Identification and SpecificationPage Overall Structure of the DE2-70 Control Panel 13. The block diagram of the DE2-70 control panel DE2-70 Video Utility Video Utility SetupDE2-70 Video Utility window VGA DisplayDisplaying selected image file on VGA Monitor Video CaptureVideo Capturing Tool Overall Structure of the DE2-70 Video UtilityVideo Capture Block Diagram Configuring the Cyclone II Fpga Using the DE2-70 BoardFpga Switch debouncing Using the LEDs and SwitchesSchematic diagram of the pushbutton and toggle switches Schematic diagram of the LEDs Pin assignments for the toggle switches Schematic diagram of the 7-segment displays Using the 7-segment DisplaysPINAD10 Clock Circuitry Block diagram of the clock distribution Lcdon Using the LCD ModuleUsing the Expansion Header JP1 PIND29 Pin assignments for the expansion headers Rset Using VGA13. VGA horizontal timing specification 11. ADV7123 pin assignments I2C Address Read is 0x34 I2C Address Write is Using the 24-bit Audio Codec10 PS/2 Serial Port RS-232 Serial PortFast Ethernet Network Controller PS/2 schematic17. Fast Ethernet schematic TV Decoder 18. TV Decoder schematic Bit VGA DAC Implementing a TV EncoderOTGD15 OTGD14 OTGD13 OTGD12 OTGD11 OTGD10 Using USB Host and DeviceUsing IrDA IrDA schematic Using SDRAM/SRAM/Flash22. Sdram schematic 23. Ssram schematic PINAA4 DRAM0CKE PINAA8 19. Sdram pin assignments SRAMDQ8 PINAK17 20. Ssram pin assignments 21. Flash pin assignments Examples of Advanced Demonstrations DE2-70 Factory ConfigurationTV Box Demonstration Block diagram of the TV box demonstration TV Box Picture in Picture PIP Demonstration Setup for the TV box demonstrationBit stream used DE270TVPIP.sof or DE270TVPIP.pof Setup for the TV box PIP demonstration USB Paintbrush Block diagram of the USB paintbrush demonstration USB Device Setup for the USB paintbrush demonstrationBlock diagram of the USB device demonstration Karaoke Machine Setup for the USB device demonstrationBit stream used DE2-70i2sound.sof or DE2-70i2sound.pof Ethernet Packet Sending/Receiving 10. The setup for the Karaoke Machine11. Packet sending and receiving using the Nios II processor SD Card Music Player 12. The setup for the Ethernet demonstration13. Block diagram of the SD music player demonstration Demonstration Setup, File Locations, and Instructions Music Synthesizer Demonstration 16 illustrates the setup for this demonstration17 illustrates the setup for this demonstration Usage of the switches, pushbuttons KEYs PS/2 Keyboard 16. The Setup of the Music Synthesizer Demonstration Nios II IDE Audio Recording and PlayingSopc Toggle switch setting for audio recorder and player Copyright Statement Revision History