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monitor. |
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| YUV 4:2:2 | SDRAM | Odd |
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TD_DATA |
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| Frame |
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| Decoder | Data Valid | Buffer |
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| Even4:2:2 | Odd4:2:2 |
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| Initiation | DLY0 |
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| DLY1 |
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| Delay |
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| Timer |
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TV |
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Decoder |
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7180 |
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TD_HS | Locked | To Control the | YUV4:2:2 |
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TD_VS | Initiation |
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Detector |
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| Sequence |
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I2C_SCLK |
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I2C_SDAT | I2C_AV |
| To |
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Config |
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| RGB |
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| Figure 6.1. Block diagram of the TV box demonstration. |
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Demonstration Setup, File Locations, and Instructions
•Project directory: DE2_70_TV
•Bit stream used: DE2_70_TV.sof or DE2_70_TV.pof
•Connect a DVD player’s composite video output (yellow plug) to the
o NTSC output
o 60 Hz refresh rate o 4:3 aspect ratio
o
•Connect the VGA output of the
•Connect the audio output of the DVD player to the
•Load the bit stream into FPGA. Press KEY0 on the
Figure 6.2 illustrates the setup for this demonstration.
68