Sigma DE2-70 manual TV Decoder schematic

Page 56

DE2-70 User Manual

V_VCC33

2

J8

VGND

VGND

 

1

 

D83

 

BAT54S

3

 

R89

36

R90

39

C26

0.1u

TD1_RESET_n

 

C27

0.1u

C28

 

 

C29

0.1u

0.1u

 

28MHZ

V_VCC33

 

 

V_VCC18

AV1_VCC18

PV1_VCC18

 

 

TD1_D[0..7]

 

 

 

 

 

 

 

14 36

 

 

27 20

 

 

C31

0.1u

 

 

 

U11

1 4

 

 

C30

 

R91

 

 

 

 

 

 

 

 

 

23

 

 

DVDD DVDD

 

DVDDIO DVDDIO

AVDD DD PV

 

19

10n

 

1.74K

AIN1

 

 

ELPF

RN44

47

 

29

 

 

 

 

AIN2

 

 

 

 

 

30

 

 

 

 

 

P0

17

1

 

16 TD1_D0

AIN3

 

 

 

 

 

 

 

 

 

 

 

 

16

2

 

15 TD1_D1

 

 

 

 

 

 

 

P1

 

31

RESET

 

 

 

 

10

3

 

14 TD1_D2

 

 

 

 

P2

 

 

 

 

 

 

9

4

 

13 TD1_D3

 

 

 

 

 

 

 

P3

 

26

 

 

 

 

 

 

8

5

 

12

TD1_D4

VREFN

 

 

 

 

P4

 

 

 

 

 

 

7

6

 

11 TD1_D5

 

 

 

 

 

 

 

P5

 

 

 

 

 

 

 

 

6

7

 

10

TD1_D6

 

 

 

 

 

 

 

P6

 

25

VREFP

 

 

 

 

5

8

 

9

TD1_D7

 

ADV7180

P7

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

XTAL

 

 

 

 

 

37

R92

 

120

TD1_VS

 

 

 

 

VS/FIELD

 

 

 

 

 

 

 

 

12

 

 

 

 

 

39

R93

 

120

TD1_HS

XTAL1

 

 

 

 

HS

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

SFL

 

 

 

 

I2C ADDRESS IS 0x40

V_VCC33

I2C_SCLK

I2C_SDAT

32

ALSB

 

 

 

38

 

 

 

 

 

 

INTRQ

 

TD1_CLK27

18

 

 

 

11

 

PWRDWN

 

LLC

 

34

 

22

 

 

SCLK

TEST_0

 

 

33

 

 

 

SDATA

 

 

 

 

 

 

 

 

ND ND ND ND SEDEXPO ND ND ND DG DG DG DG AG AG AG

 

 

 

315354041212428

VGND

V_VCC33

VGND

 

2

1

 

 

D84

 

 

BAT54S

J9

3

 

R94

36

 

RCA JACK

R95

39

 

VGND

 

 

C32

0.1u

TD2_RESET_n

C33

0.1u

C34

 

 

C35

0.1u

0.1u

 

28MHZ

23

29

30 31

26

25 13

 

 

V_VCC33

 

 

 

 

 

 

TD2_D[0..7]

 

V_VCC18

AV2_VCC18

 

PV2_VCC18

 

 

 

 

14 36

 

 

27 20

 

 

C37

0.1u

 

 

U12

1 4

 

 

C36

 

R96

 

 

 

 

 

 

 

 

 

 

DVDD DVDD

 

VDDIO DVDDIO D

AVDD PVDD

 

19

10n

 

1.74K

AIN1

 

 

ELPF

RN45

47

 

 

 

 

 

AIN2

 

 

 

17

TD2_D0

 

 

 

 

 

P0

1

 

16

AIN3

 

 

 

 

 

 

 

 

 

 

 

16

2

 

15

TD2_D1

 

 

 

 

 

 

P1

 

 

 

 

 

 

 

10

3

 

14

TD2_D2

RESET

 

 

 

 

P2

 

 

 

 

 

9

4

 

13

TD2_D3

 

 

 

 

 

 

P3

 

 

 

 

 

 

 

8

5

 

12

TD2_D4

VREFN

 

 

 

 

P4

 

 

 

 

 

7

6

 

11

TD2_D5

 

 

 

 

 

 

P5

 

 

 

 

 

 

 

6

7

 

10

TD2_D6

 

 

 

 

 

 

P6

 

 

 

 

 

 

 

5

8

 

9

TD2_D7

VREFP

 

ADV7180

P7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL

 

 

 

VS/FIELD

37

R97

 

120

TD2_VS

 

 

 

 

 

 

I2C ADDRESS IS 0x42

V_VCC33

 

I2C_SCLK

I2C_SDAT

12 32

18

34 33

XTAL1

 

HS

39

R98

120 TD2_HS

 

2

 

 

 

 

 

 

 

 

SFL

 

 

 

 

 

 

ALSB

 

38

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTRQ

 

 

 

TD2_CLK27

 

 

11

 

 

 

PWRDWN

 

LLC

 

 

 

 

22

 

 

 

 

 

 

SCLK

TEST_0

 

 

 

 

 

 

 

 

 

 

 

 

 

SDATA

 

 

 

 

 

 

 

 

 

 

ND ND ND ND SEDEXPO ND ND ND DG DG DG DG AG AG AG

 

 

 

 

 

 

 

315354041212428

 

 

VGND

 

Figure 5.18. TV Decoder schematic.

 

 

 

Signal Name

FPGA Pin No.

Description

 

 

 

TD1_D[0]

PIN_A6

TV Decoder 1 Data[0]

 

 

 

TD1_D[1]

PIN_B6

TV Decoder 1 Data[1]

 

 

 

TD1_D[2]

PIN_A5

TV Decoder 1 Data[2]

 

 

 

TD1_D[3]

PIN_B5

TV Decoder 1 Data[3]

 

 

 

TD1_D[4]

PIN_B4

TV Decoder 1 Data[4]

 

 

 

TD1_D[5]

PIN_C4

TV Decoder 1 Data[5]

 

 

 

TD1_D[6]

PIN_A3

TV Decoder 1 Data[6]

 

 

 

TD1_D[7]

PIN_B3

TV Decoder 1 Data[7]

 

 

 

TD1_HS

PIN_E13

TV Decoder 1 H_SYNC

 

 

 

TD1_VS

PIN_E14

TV Decoder 1 V_SYNC

 

 

 

53

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Contents Copyright 2007 Terasic Technologies Contents Appendix Package Contents DE2-70 PackageDE2-70 Board Assembly Feet for the DE2-70 boardGetting Help Altera DE2-70 Board Layout and ComponentsBlock Diagram of the DE2-70 Board Cyclone II 2C70 Fpga Ssram Audio Codec Power-up the DE2-70 Board Serial portsLCD display shows Welcome to the Altera DE2-70 Control Panel Setup DE2-70 Control PanelPage Controlling the LEDs, 7-Segment Displays and LCD Display Controlling 7-SEG display Switches and Buttons SDRAM/SSRAM/Flash Controller and Programmer Page Press Load Memory Content to a File button USB MonitoringPS2 Device USB Mouse Monitoring ToolSD Card 10. Reading the SD card Identification and Specification Audio Playing and RecordingPage Overall Structure of the DE2-70 Control Panel 13. The block diagram of the DE2-70 control panel Video Utility Setup DE2-70 Video UtilityVGA Display DE2-70 Video Utility windowVideo Capture Displaying selected image file on VGA MonitorOverall Structure of the DE2-70 Video Utility Video Capturing ToolVideo Capture Block Diagram Using the DE2-70 Board Configuring the Cyclone II FpgaFpga Using the LEDs and Switches Switch debouncingSchematic diagram of the pushbutton and toggle switches Schematic diagram of the LEDs Pin assignments for the toggle switches Using the 7-segment Displays Schematic diagram of the 7-segment displaysPINAD10 Clock Circuitry Block diagram of the clock distribution Using the LCD Module LcdonUsing the Expansion Header JP1 PIND29 Pin assignments for the expansion headers Using VGA Rset13. VGA horizontal timing specification 11. ADV7123 pin assignments Using the 24-bit Audio Codec I2C Address Read is 0x34 I2C Address Write isRS-232 Serial Port 10 PS/2 Serial PortPS/2 schematic Fast Ethernet Network Controller17. Fast Ethernet schematic TV Decoder 18. TV Decoder schematic Implementing a TV Encoder Bit VGA DACUsing USB Host and Device OTGD15 OTGD14 OTGD13 OTGD12 OTGD11 OTGD10Using IrDA Using SDRAM/SRAM/Flash IrDA schematic22. Sdram schematic 23. Ssram schematic PINAA4 DRAM0CKE PINAA8 19. Sdram pin assignments SRAMDQ8 PINAK17 20. Ssram pin assignments 21. Flash pin assignments DE2-70 Factory Configuration Examples of Advanced DemonstrationsTV Box Demonstration Block diagram of the TV box demonstration Setup for the TV box demonstration TV Box Picture in Picture PIP DemonstrationBit stream used DE270TVPIP.sof or DE270TVPIP.pof Setup for the TV box PIP demonstration USB Paintbrush Block diagram of the USB paintbrush demonstration Setup for the USB paintbrush demonstration USB DeviceBlock diagram of the USB device demonstration Setup for the USB device demonstration Karaoke MachineBit stream used DE2-70i2sound.sof or DE2-70i2sound.pof 10. The setup for the Karaoke Machine Ethernet Packet Sending/Receiving11. Packet sending and receiving using the Nios II processor 12. The setup for the Ethernet demonstration SD Card Music Player13. Block diagram of the SD music player demonstration Demonstration Setup, File Locations, and Instructions 16 illustrates the setup for this demonstration Music Synthesizer Demonstration17 illustrates the setup for this demonstration Usage of the switches, pushbuttons KEYs PS/2 Keyboard 16. The Setup of the Music Synthesizer Demonstration Audio Recording and Playing Nios II IDESopc Toggle switch setting for audio recorder and player Revision History Copyright Statement
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